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Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，...

于 2022-03-21 发布文件大小:1,002.00 B

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Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,

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svtb_ahb_sram
说明：一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)

2020-06-30 13:40:02下载

积分：1
CORDIC FPGA使用Verilog程序实现
cordic的verilog程序用ＦＰＧＡ实现-CORDIC FPGA using the Verilog procedures realize

2022-05-29 16:40:15下载

积分：1
8位大小比较器
说明： 8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)

2005-10-28 22:35:12下载

积分：1
here is realized simple FIFO stack in vhdl. very simple example, but very help...
here is realized simple FIFO stack in vhdl. very simple example, but very helpful.

2022-03-12 07:44:59下载

积分：1
斯巴达3 Digilent演示：演示驱动perphrials在斯巴达3板的…
Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.

2023-08-14 05:45:04下载

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I2C
说明： iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现(iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation)

2011-04-02 10:04:36下载

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任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。...
任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.

2022-08-10 12:37:41下载

积分：1
RS-422standardmodulev2
rs422标准通讯模块异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

2013-12-23 14:14:18下载

积分：1
float_int
自己编写的，浮点数与整数之间的转换的Verilog HDL实现(Written by myself, it is converted into Verilog HDL integer floating point implementation)

2020-12-18 10:29:11下载

积分：1
dct01
Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)

2011-01-17 02:40:41下载

积分：1

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Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，...

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