-
AX301
黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301(Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301)
- 2021-03-23 21:59:15下载
- 积分:1
-
UART to send the complete procedure, including the complete source code of nucle...
UART的完整发送程序,包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.
- 2022-01-28 15:16:09下载
- 积分:1
-
dct_verilog
用FPGA实现dct变换。verilog语言实现,在quartus9.0中验证,含整个工程(dct transform verilog language in quartus9.0 verify, with the entire project)
- 2020-12-02 18:59:24下载
- 积分:1
-
nor_flash_core
Verilog实现的NOR FLASH控制器,基于M25P128开发,功能完整,简洁易懂,自用无问题。(Verilog implementations NOR FLASH controller, based M25P128 development, full-featured, easy to read, for personal use, no problem.)
- 2021-03-09 14:09:27下载
- 积分:1
-
UC3842
基于uc3842的反激电路的saber仿真模型,可调制,波形结果完美(The saber of the flyback circuit simulation model based on uc3842, modulation, waveform perfect results)
- 2015-05-06 21:52:14下载
- 积分:1
-
system
清华大学电子课程设计:Verilog,QuartusII可正确运行,可下载到FPGA上,完成远程通信的整体任务,PC发数据,键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机,需异步串口调试软件(Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and operands calculation displays the results in digital tube and returned to the PC, to be asynchronous serial debugging software)
- 2020-08-16 23:38:25下载
- 积分:1
-
verilog 编写基于SRAM(CY7C1041)的代码
verilog 编写基于SRAM(CY7C1041)的代码-Verilog prepared based on the SRAM (CY7C1041) code
- 2022-07-05 00:16:39下载
- 积分:1
-
FM
说明: 基于FPGA和弦!!!音乐芯片的设计与实现!!!(Design and implementation of FPGA chip based on the chord music)
- 2015-01-07 17:02:29下载
- 积分:1
-
使用Virtex-5 FPGA高级加密标准算法的高效实现
应用背景在本文中,一个高性能和高度优化Rijndael AES算法的硬件实现了设计并实现Xilinx Virtex-5 xc5vlx50FPGA器件。设计采用模块化利用VHDL语言的方法。设计工作正确如图所示。这个所提出的设计的性能进行评估的基础上吞吐量和面积。我们的设计利用了速度339.087兆赫,这意味着吞吐量4.34用399片Virtex-5 FPGA面积Gbps。关键技术本文提出了一种有效的Rijndael算法的硬件实现高级加密标准(AES)加密算法采用最先进的现场可编程门阵列(FPGA)。在非常高速集成电路设计的设计硬件描述语言(VHDL)。时序仿真进行验证所设计的电路的功能。性能评估也做了吞吐量和区域。在国家的最先进的Xilinx Virtex-5实现设计(xc5vlx50ffg676-3)FPGA实现吞吐量4.34千兆位/秒,总共使用了399片。
- 2022-02-20 11:10:20下载
- 积分:1
-
weifenqi
微分器:利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)
- 2020-12-01 10:39:28下载
- 积分:1