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design through verilog hdl
design through verilog hdl
- 2023-04-07 06:25:04下载
- 积分:1
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This is what I found online vhdl language used to write the sdram controller cod...
这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱:wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
- 2022-03-26 03:30:04下载
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altera详细使用配置手册,有一定的参考价值,写的比较详细
altera详细使用配置手册,有一定的参考价值,写的比较详细-altera in detail the use of manual configuration, has a certain reference value, a more detailed written
- 2022-03-20 13:35:35下载
- 积分:1
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HalfbandDec
基于FPGA开发的11阶半带升余弦FIR滤波器,用在阅读器基带滤波时的抽取滤波器使用,采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)
- 2012-10-25 11:18:40下载
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VHDL采用I2C控制器,是一个组件,你可以使用添加之间。
用VHDL制作的I2C控制器,是一个component,之间添加就可以使用。-VHDL produced using I2C controller, is a component, you can use to add between.
- 2022-06-18 14:45:04下载
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AD7608
8通道同步AD芯片7608的FPGA控制程序(FPGA control program of ad7608(8 channel synchronous AD chip))
- 2021-03-13 12:09:24下载
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FPGA
说明: 基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)
- 2010-04-16 19:40:41下载
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HwLog10
用verilog写的,基于查表法实现的LOG10运算器,在Altera FPGA中应用。(It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.)
- 2021-04-07 15:59:01下载
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LFM
该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
- 2021-04-19 09:38:51下载
- 积分:1
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Quartus II TimeQuest时序分析器说明书
说明: Quartus II TimeQuest 时序分析器说明书;这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识,以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)
- 2020-08-07 17:48:31下载
- 积分:1