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viterbi_soft
维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA(viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA)
- 2021-01-17 22:58:46下载
- 积分：1
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rc-evga-indtube
evga-indtube.h - Keytable for evga_indtube Remote Controller.
- 2015-04-16 11:06:12下载
- 积分：1
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Continuous_delay_control_Farrow
说明： matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
- 2019-06-14 09:10:59下载
- 积分：1
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grain-128a
基于grain-128a算法的流加密模块(Stream encryption module based on grain-128a algorithm)
- 2020-07-04 12:20:01下载
- 积分：1
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RTC
verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)
- 2009-12-19 23:51:50下载
- 积分：1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分：1
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20190718 - Copy
说明： this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device
- 2020-06-21 21:20:02下载
- 积分：1
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vga_driver
verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)
- 2016-05-25 17:19:18下载
- 积分：1
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EPM570
非常好的EPM570(CPLD)学习程序源码,适合初学者,能让其快速入门(Very good EPM570 (CPLD) learning program source code, suitable for beginners, allowing its Quick Start)
- 2013-09-11 10:18:59下载
- 积分：1
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uart
说明： uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)
- 2020-06-20 20:00:02下载
- 积分：1
