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tdc
time to digital convertor
- 2011-09-22 16:25:50下载
- 积分:1
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有限状态机 — FSM
有限状态机是指输出取决于过去输入部分和当前输入部分是时序逻辑电路。在有限状态机中,状态寄存器的下一个状态不仅与输入信号有关,而且还与该寄存器的当前输入有关,因此有限状态机又可以认为是组合逻辑和寄存器逻辑的一中组合。下面代码是哈工大计算机学院CPU设计中关于有限状态机部分的代码。
- 2022-07-18 13:01:32下载
- 积分:1
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tcdg
Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.
- 2014-01-29 15:57:35下载
- 积分:1
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脉冲多普勒雷达回波信号相干积累的VHDL源程序(pulse Doppler radar echo signal coherent accumulation of VHDL source)
- 2021-04-22 20:28:48下载
- 积分:1
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EnDat
ENDAT 协议说明,包括时序等详细的说明,(endat Encoder characteristics)
- 2021-05-12 22:30:02下载
- 积分:1
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如果不考虑占空比,直接利用计数器来进行分频,则占空比会发生变化。下面程序实现1:1的三分频。...
如果不考虑占空比,直接利用计数器来进行分频,则占空比会发生变化。下面程序实现1:1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.
- 2022-01-21 05:34:37下载
- 积分:1
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一种学习用的小程序,主要用与VHDL仿真的全加器的一段代码!大家可以下载进行修改于仿写...
一种学习用的小程序,主要用与VHDL仿真的全加器的一段代码!大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie
- 2022-01-25 21:36:29下载
- 积分:1
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基于ALtera公司的若干款FPGA的调试经验,对初学者有重要价值
基于ALtera公司的若干款FPGA的调试经验,对初学者有重要价值-ALtera a number of sections based on the company" s FPGA debugging experience, great value for beginners
- 2022-05-19 11:30:26下载
- 积分:1
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7SegmenAngka
说明: asssembly ccode to turn on 7 segmen
- 2019-12-17 09:53:09下载
- 积分:1
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KEY SCAN VHDL
自己写的键盘的扫描4乘4的键盘VHDL 很好用的-KEY SCAN VHDL
- 2022-07-16 19:10:38下载
- 积分:1