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RS-encode_FPGA
利用FPGA开发软件 进行rs编码的仿真 模拟RS编码的过程步骤(rs code in FPGA)
- 2012-04-21 21:00:28下载
- 积分：1
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This document gives the code for programming a CC2500 transceiver using Altera S...
This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
- 2022-02-26 15:59:21下载
- 积分：1
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qianzhaowang
一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分：1
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ahb_sramc_svtb
ahb总线Verilog代码及sv仿真文件(ahb bus Verilog code and sv simulation code)
- 2021-05-14 14:30:02下载
- 积分：1
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Great guide for writing VHDL
Great guide for writing VHDL
- 2023-05-21 15:20:03下载
- 积分：1
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fpga
Once the FPGA is located, the rest of the mapping data for the other components can be determined dynamically its section mapping registers.
- 2015-11-05 20:55:50下载
- 积分：1
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一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形...
一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source
- 2022-02-19 22:00:27下载
- 积分：1
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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分：1
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raised-cosine-filter
代码实现了一个根升余弦成型滤波器，2PAM信号通过此成型滤波器，并且匹配接收，画出了发送和接收波形，验证了代码的正确性。(The code designs a root raised cosine filter,2PAM signal transmitted through the filter and matched using the same filter, I plot the transmitted signal and received signal to verify the correctness of the code.)
- 2012-11-09 21:59:53下载
- 积分：1
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data_rom
正弦信号发生器，用VHDL来完成，抗干扰能力较强，(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)
- 2009-07-15 22:44:02下载
- 积分：1
