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ad9226
FPGA驱动adc9226，高精度高速度。(ad9226 by FPGA)
- 2015-08-04 10:03:20下载
- 积分：1
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: Random pulse width modulation speed control system to solve the exchange of ac...
：随机脉宽调制是解决交流调速系统 中声学噪声的直接有效方法。随机零矢 量分 布是一种很好 的随
机方法，但其不对称的开关函数使其不适用于传统的电流采样方法。通过仿真表明 PWM周期中点采样的方
法无法得到准确的平均值，在分析不对称模式引起的纹波电流对电流平均值影响的基础上，提出了一种适合
于 RZV分布 的电流采样方法 。仿真结果证实该方法简单可行 。 -: Random pulse width modulation speed control system to solve the exchange of acoustic noise in a direct and effective way. Random zero vector distribution is a good random method, but the asymmetrical switching function so that it does not apply to the traditional current sampling methods. PWM cycle through the simulation shows that the mid-point sampling methods can not be an accurate, on average, the analysis of asymmetric mode ripple current caused by the impact on the current average value based on the proposed distribution of a suitable RZV current sampling methods. The simulation results confirmed that the method is simple and feasible.
- 2022-04-24 11:00:11下载
- 积分：1
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关于VHDL编程的教程,比较系统的讲解,很有用的书
关于VHDL编程的教程,比较系统的讲解,很有用的书-a book about VHDL
- 2022-01-26 14:49:07下载
- 积分：1
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axi_master
自己写的 AXI master code(AXI master code)
- 2014-10-20 15:53:41下载
- 积分：1
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ise
xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)
- 2007-09-20 14:30:52下载
- 积分：1
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Application of VHDL language of the control procedures of traffic lights. Famili...
应用VHDL语言编写交通灯的控制程序。 熟悉该语言的基本用法。-Application of VHDL language of the control procedures of traffic lights. Familiar with the basic use of the language.
- 2023-07-22 01:45:04下载
- 积分：1
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TCD1304_drive
FPGA驱动TCD1304AP线阵CCD，并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)
- 2021-05-15 18:30:02下载
- 积分：1
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LDPC_Encoder
说明： verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)
- 2021-03-08 19:19:28下载
- 积分：1
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PiSo
8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)
- 2020-11-30 21:59:27下载
- 积分：1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分：1
