-
FPGA设计软件的绝佳入门书籍,本人珍藏,全部吐血奉献之2,请大家赶紧下!...
FPGA设计软件的绝佳入门书籍,本人珍藏,全部吐血奉献之2,请大家赶紧下!-FPGA design software, an excellent entry-books, I treasure all the blood sacrifice of 2, please hurry under the U.S.!
- 2022-07-17 20:40:02下载
- 积分:1
-
模糊控制器verilog程序代码
说明: 模糊控制器verilog程序,模糊控制器最简单的实现方法是将一系列模糊控制规则离线转化为一个查询表(又称为控制表)。这种模糊控制其结构简单,使用方便,是最基本的一种形式。(Verilog program of fuzzy controller)
- 2020-04-14 12:04:52下载
- 积分:1
-
4dbpsk系统的设计实现源码,几个朋友用一个假期的时间协作完成,功能非常好...
4dbpsk系统的设计实现源码,几个朋友用一个假期的时间协作完成,功能非常好-The 4dbpsk system design realization source code, several friends complete it cooperation in one vacation time , the function is extremely good
- 2022-02-04 07:05:28下载
- 积分:1
-
vhdl-cordic-atan-master
说明: Implementation of CORDIC atan block in VHDL
- 2019-05-14 16:51:26下载
- 积分:1
-
学习Xilinx公司开发软件ISE的基础资料,从最基础到复杂逻辑设计。
学习Xilinx公司开发软件ISE的基础资料,从最基础到复杂逻辑设计。-Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.
- 2022-05-27 10:26:09下载
- 积分:1
-
usb_test
Cypress USB 的主从FPGA 控制实现代码(USB controller)
- 2012-10-09 10:39:52下载
- 积分:1
-
80211_Transmitter_VerilogHDL
802.11a Transmitter implementation Using Verilog
- 2021-01-20 15:28:41下载
- 积分:1
-
FPGA实现Jpeg压缩,和视频采集程序
说明: FPGA实现Jpeg压缩,和视频采集程序(Zynq - Main - register access Mio)
- 2020-03-13 23:25:40下载
- 积分:1
-
adc0809
1、用状态机设计A/D转换器ADC0809的采样控制电路,并在数码管上显示转换结果;
2、设置有复位和启动/保持开关,要求
⑴ 复位开关用来使A/D转换器复位,并做好A/D转换准备;
⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果,即按一下启动/保持开关,启动A/D转换器开始转换,再按一下启/停开关,停止转换并保持结果。
3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)
- 2021-01-02 21:38:57下载
- 积分:1
-
traffic_lights
交通灯控制器控制红(r)、绿(g)、黄(y)三种不同颜色的交通灯,这三种不同颜色灯的亮、灭分别由三个定时器(timer1、timer2、timer3)控制;
当某个定时器工作时,它所控制的交通灯亮,直到设定的定时时间到(该定时器状态由’0’变’1’),交通灯跳转到另一种状态;
clk是脉冲控制端(图中未标出);reset是异步复位端,复位状态为红色交通灯亮;
输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。
( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights output terminal r, g, y represent the three colors of traffic lights bright, the off state.)
- 2020-12-19 15:09:10下载
- 积分:1