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sqr
VHDL CODE FOR SQUARE WAVE GENERATOR
- 2014-01-22 17:14:20下载
- 积分：1
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DDS_DAC_Output
说明： 本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)
- 2019-05-06 10:05:10下载
- 积分：1
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Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen
利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen
- 2023-04-13 10:15:04下载
- 积分：1
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dpll
数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)
- 2017-04-04 23:13:28下载
- 积分：1
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四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D...
四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
- 2023-04-13 16:10:03下载
- 积分：1
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beep_interface
这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)
- 2013-05-05 21:07:18下载
- 积分：1
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有关视频压缩的IPCore，希望对大家有用
有关视频压缩的IPCore，希望对大家有用-Video Compression IPCore
- 2022-09-14 19:10:03下载
- 积分：1
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I2C
VHDL语言编写的I2C通信接口,可与单片机等MCU相连,只占用很少的引脚线完成数据的传输(Written in VHDL I2C communication interface, such as MCU and MCU can be connected, only takes a few lines to complete the data transmission pin)
- 2011-05-15 09:00:33下载
- 积分：1
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FIR低
fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
- 2023-05-01 00:45:03下载
- 积分：1
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VHDL语言程序集。PDF格式，所有的例子，你将看不到偷…
vhdl语言例程集锦.pdf，全部的例子，看你会不会偷了-VHDL language routines Collection. pdf, all the examples, you will not see stealing
- 2022-02-11 21:16:40下载
- 积分：1
