登录
首页 » VHDL » VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。...

VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。...

于 2022-03-26 发布 文件大小:180.37 kB
0 152
下载积分: 2 下载次数: 1

代码说明:

VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。-VHDL development environment, taxi billing system to achieve the initial 10 yuan for each additional mile, automatic up 2.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • CXFlt
    通信系统中的基带信号处理中的成型滤波器代码,已经通过编译。(Communication system baseband signal processing shaping filter code, has passed the compilation.)
    2015-03-24 09:43:05下载
    积分:1
  • 基于VHDL语言的循环码编码器的程序,以一个(15,6)循环码为例...
    基于VHDL语言的循环码编码器的程序,以一个(15,6)循环码为例-VHDL language based on the cycle of the program code encoder to a (15,6) cyclic code as an example
    2022-03-13 14:13:18下载
    积分:1
  • 实现一个简单的电子钟,时间(小时,分,秒)可以设置…
    实现一个简单的电子钟,其时间(时,分,秒)可以设置和更改,设置和更改的同时不会影响其他显示的变化(相互独立)。-achieve a simple electronic bell, the time (hours, minutes and seconds) can set and change, Settings and change will not affect the other shows the change (independent).
    2022-04-07 20:02:24下载
    积分:1
  • AD9226
    一个AD9226芯片的驱动,用FPGA写的。虽然简单,但是希望对各位有帮助(An AD9226 chip driver, FPGA written. Though simple, but I hope you will help)
    2013-09-05 01:47:36下载
    积分:1
  • ADS8509
    FPGA驱动高输入电压范围的ADS8509芯片,采样范围广,适合前端大信号处理(FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing)
    2015-08-10 22:03:59下载
    积分:1
  • 程序
    传感器是一种检测装置,能感受到被测量的信息,并能将感受到的信息,按一定规律变换成为电信号或其他所需形式的信息输出,以满足信息的传输、处理、存储、显示、记录和控制等要求(Sensor is a kind of detection device, which can sense the measured information and transform it into electrical signal or other required information output according to certain rules to meet the requirements of information transmission, processing, storage, display, recording and control.)
    2020-06-18 22:00:01下载
    积分:1
  • verilog时钟分频器~ 50hmz波特率9600bps,使用~
    verilog分频器~时钟为50hmz,波特率采用9600bps~-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
    2022-06-03 13:21:28下载
    积分:1
  • C54x is the Verilog code opencoreip
    c54x的VeriLog程序代码 也是opencoreip-C54x is the Verilog code opencoreip
    2022-03-26 18:08:34下载
    积分:1
  • FirlterTeam
    数字滤波器组。包含matlab程序和word说明。通过一个低通数字滤波器和多个带通数字滤波器组合成一个滤波器组(Groups of the digital filter. Contains matlab program and word description. Through the combination of a low pass digital filter, and a plurality of band-pass digital filter into a filter bank)
    2013-01-15 20:38:33下载
    积分:1
  • P2S
    Parallel to Serial converter Module
    2013-07-27 18:06:44下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载