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vhdl
vhdl表示与综合，原书第二版，中文版，比较全，用超星打开-vhdl
- 2023-05-18 10:30:04下载
- 积分：1
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Lab5.5_Led_FPGA
使用verilog在fpga开发板实现流水灯，包括整个工程文件(This code is used for early learners to study verilog。)
- 2014-05-07 19:57:24下载
- 积分：1
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Coding Style
说明： 良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)
- 2020-06-17 12:00:01下载
- 积分：1
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Can be directly downloaded to the chip used in the complete UART with FIFO proce...
可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.
- 2022-05-23 23:16:30下载
- 积分：1
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My-Simple-Specturm--Analyzer
基于LabVIEW FPGA的频谱估计与分析(the power spectrum estimation and analysis based on LabVIEW FPGA)
- 2013-11-13 08:45:40下载
- 积分：1
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Asynchronous FIFO controller Verilog Design and Implementation
异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
- 2022-08-14 15:39:50下载
- 积分：1
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DigitalClock
数字钟：实验中用到的小程序，用于万年历中的模块(Digital clock: a small program used in the experiment, the modules for calendar)
- 2013-05-26 09:25:23下载
- 积分：1
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my_test_rw_pack9
基于Verilog HDL的SDRAM控制器。
实验条件：
工具：Quartus II 6.0 ,SignalTap II
FPGA：Altera Cyclone EP1C12Q240C8N
SDRAM：HY57V283220T-6(SDRAM controller based on Verilog HDL.
Experimental conditions:
Tools: Quartus II 6.0, SignalTap II
FPGA: Altera Cyclone EP1C12Q240C8N
SDRAM: HY57V283220T-6)
- 2013-01-31 11:13:26下载
- 积分：1
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i2c-configure-SAA7113
i2c配置SAA7113，非常有用的程序，做视频采集类必看(i2c configure SAA7113)
- 2013-12-25 16:37:37下载
- 积分：1
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The use of Altera' s FPGA
使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
- 2022-08-23 17:16:15下载
- 积分：1
