登录
首页 » VHDL » VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。...

VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。...

于 2022-03-26 发布 文件大小:180.37 kB
0 122
下载积分: 2 下载次数: 1

代码说明:

VHDL开发环境,出租车计费系统,实现起步10元,每增加一公里,自动上涨2元。-VHDL development environment, taxi billing system to achieve the initial 10 yuan for each additional mile, automatic up 2.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • COSTAS_LOOP
    用verilog编写的科斯塔斯环,希望有帮助(Costas loop written in verilog helpful)
    2012-10-31 23:01:23下载
    积分:1
  • 4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率....
    4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.
    2022-04-20 03:37:20下载
    积分:1
  • ALU用VHDL项目
    ALU using VHDL project
    2022-03-22 23:35:27下载
    积分:1
  • E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
    E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
    2023-06-23 08:30:04下载
    积分:1
  • weifen-program
    基于FPGA微分程序代码及其电路驱动程序(Based on FPGA differential program )
    2011-12-19 12:17:59下载
    积分:1
  • 测试VANET应用程序
    他延误用户inrandom经历过或基于竞争的MAC方案是无界;用户可能需要等待论坛很长一段时间,直到他/她发送一些数据的机会。在otherhand,通过根据一定的deterministicpattern,这被称为由梅西和马特仕协议序列调度所述数据分组,延迟的hardguarantee可以完成。
    2022-07-10 10:09:43下载
    积分:1
  • matlab-genetic-algorithm
    matlab用法 主要用于线性规划,非线性规划,解决优化问题,作出最合理的决策等遗传算法程序(matlab usage is mainly used for linear programming, nonlinear programming to solve optimization problems, make the most rational decision-making, genetic algorithm)
    2011-09-08 10:34:43下载
    积分:1
  • SPI
    design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
    2010-08-17 19:16:12下载
    积分:1
  • VHDL implement serial port, it can communicate with pc, it can accept and send m...
    用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
    2022-02-11 22:49:32下载
    积分:1
  • fifo_rs232
    从FIFO到到RS232的实现,用于接收和缓存数据(TripAdvisor RS232 FIFO implementation for receiving data and cache)
    2016-08-26 13:57:23下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载