-
zzlB
QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
)
- 2011-12-21 16:17:41下载
- 积分：1
-
Walsh
沃尔什函数序列sequency的verilog编程实现，含有测试文件(the Walsh sequence in sequency order)
- 2020-07-03 08:20:01下载
- 积分：1
-
pipline_lms_and_rls_verilog
流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)
- 2021-05-06 20:58:37下载
- 积分：1
-
VHDL
Project manager is reak vhdl old man
- 2015-09-10 10:06:28下载
- 积分：1
-
20081209_Test_maus
Its project to move your mouse cursor on a vga monitor. it is very funny -)(Its project to move your mouse cursor on a vga monitor. it is very funny -))
- 2009-05-12 18:53:12下载
- 积分：1
-
华为 Verilog基本电路设计指导书
说明： 华为 Verilog基本电路设计指导书--本文列举了大量的基本电路的Verilog HDL 代码，使初学者能够迅速熟悉基本的HDL 建模；同时也列举了一些常用电路的代码(Huawei Verilog basic circuit design instruction)
- 2020-07-04 11:00:01下载
- 积分：1
-
gtx_aurora_zc706_example
Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议，通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式，以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enables data transfer between two devices over one or more serial links. Protocol Aurora protocol can support two data transfer modes, stream and frame, as well as full-duplex, simplex and other data communications.)
- 2018-01-23 08:53:37下载
- 积分：1
-
九层单个电梯的控制系统设计和测试代码rar
说明： 这是一个单个的九层的电梯控制系统的VHDL代码，具有外部上下楼控制按钮和内部上下楼控制按钮。另外还有测试代码。(This is a design of nine floor lift control system with VHDL code and testbench.)
- 2020-06-19 22:03:11下载
- 积分：1
-
DDSverilog
说明： 基于FPGA的Veilog HDL实现代码，简单明了，希望能帮助verilog的初学者……(ＤＤＳ based on Verilog ＤＨＬ for FPGA )
- 2011-04-11 22:56:23下载
- 积分：1
-
fsm
有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)
- 2010-02-13 17:46:25下载
- 积分：1
