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DE2_115_TV
DE2-115开发板TV摄像头成像程序，源码亲测可用，可加入边缘算法成像，实时显示轮廓，速度流畅(The DE2-115 development board TV camera imaging procedures, the pro-test in the source can be added to the edge algorithms imaging, real-time display contours, fast-paced)
- 2020-07-09 19:18:55下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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实例
FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)
- 2020-06-22 22:40:02下载
- 积分：1
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gold
基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)
- 2011-05-16 21:48:38下载
- 积分：1
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汉明码
16 位海明编码器是写的 verilog 语言，它将在 Xlinx 工具中成功运行，并给出结果。基本上海明编码器用于通信领域，其中的数据进行加密和传输到接收器，有助于数据的安全性。
- 2022-03-19 06:33:02下载
- 积分：1
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NiosII_mycpu
基于NiosII 的SOC FPGA验证系统，适用初学者学习Altra Quartus II软件，以及C语言 veriog，以及MCU调试流程
- 2022-03-19 06:31:20下载
- 积分：1
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基于Nios II checksum利用 altera的验证C2H accelerator的系统-Cyclone II
基于Nios II checksum利用 altera的验证C2H accelerator的系统，已用DE-2 board 验证过，
里面还有DMA 方式的 component，Software Code, Custom Instruction, 和普通的component 各做了比较。
对想了解NiosII 系统的应该有很大的帮助。
- 2022-11-11 10:05:08下载
- 积分：1
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chaoshengbo_diatance_hc_sr_04
实现Verilog编程，实现超声波测距模块实现测距功能，并将测得的距离显示在数码管上(Verilog programming is realized, ultrasonic ranging module is realized, and the measured distance is displayed on the digital tube)
- 2020-06-17 16:40:02下载
- 积分：1
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明德扬科教之Gvim_20170511
FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)
- 2021-04-14 19:58:55下载
- 积分：1
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uart
用Verilog HDL，实现的FPGA串口调试程序，已经在硬件上调试成功(With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful)
- 2015-07-23 15:24:12下载
- 积分：1
