-
FPGA
基于FPGA与LM4550B的AC97软声卡VHDL语言驱动,版本2.0-FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0
- 2022-10-28 20:25:03下载
- 积分:1
-
VHDL Digital Full ADDER Logic Program
- 2022-08-03 08:35:11下载
- 积分:1
-
verilog编写随机数产生源程序,在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的...
verilog编写随机数产生源程序,在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
- 2023-03-24 01:00:04下载
- 积分:1
-
Clifford-E.-Cummings-paper
Clifford E. Cummings论文合集,其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)
- 2012-07-21 01:32:34下载
- 积分:1
-
20181060261-李康_3
说明: 秒表的实现,有暂停清零功能,Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分:1
-
FPGA_MVB
此论文想详细阐明了用FPGA做硬件处理,集成SOPC功能实现MVB通讯协议的解决方案,可以运行在alter fpga上面。(This paper expounds in detail the processing to do with FPGA hardware, integrated solutions for SOPC function of the realization of MVB communication protocol, can run in alter FPGA above.)
- 2021-01-03 17:58:56下载
- 积分:1
-
Describes how to use VHDL language processor spi interface
介绍了如何用vhdl语言实现处理器的spi接口-Describes how to use VHDL language processor spi interface
- 2022-07-22 21:57:12下载
- 积分:1
-
SimpleVOut-master
说明: SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分:1
-
sdram-control-verilog
SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。(This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.)
- 2009-12-11 15:01:46下载
- 积分:1
-
vhdl的基础性的介绍,对初学者大有用处
vhdl的基础性的介绍,对初学者大有用处-vhdl basic introduction
- 2022-05-20 01:22:09下载
- 积分:1