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篮球24秒可控计时器设计
用VHDL语言设计篮球24秒可控计时器功能说明:1.具有24秒计时、显示功能; 2.设置外部按键,完成清零、暂停、恢复控制; 3.24秒倒计时,时间间隔为1s; 4.时间到后发出报警信号,并在3s后解除。
- 2022-05-28 22:06:17下载
- 积分:1
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QPSK_DDS
说明: Implementing QPSK using DSS
- 2020-01-14 06:00:57下载
- 积分:1
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HDMI_IP
说明: HDMI IP的verilog实现,vivado平台生成的IP核(Verilog implementation of HDMI IP)
- 2020-03-30 14:38:56下载
- 积分:1
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用FPGA实现CRC算法,只用一个脉冲就能实现,比传统的移位算法大大节约时间...
用FPGA实现CRC算法,只用一个脉冲就能实现,比传统的移位算法大大节约时间-Using FPGA to achieve CRC algorithm, only one pulse will be able to realize, than the traditional algorithm greatly saving time shift
- 2022-07-14 15:39:31下载
- 积分:1
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verilog
关于USB开发的verilog开发程序,非常的全面,学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)
- 2013-12-26 18:29:35下载
- 积分:1
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UART_prj_ViHDL
vhdl project at sbu uni in iran
uart
- 2010-05-08 16:18:37下载
- 积分:1
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中值滤波算法
中值滤波实现。选择在Vivado软件上采用Verilog语言来编写中值滤波算法,搭建出完整的数据处理系统架构,通过仿真和验证来判断数据的处理效果,并在实际的设计过程中根据出现的问题提出解决方案。(Median filter implementation. The author chose Verilog language to write the median filter algorithm in Vivado software, built a complete data processing system architecture, judged the data processing effect through simulation and verification, and proposed a solution according to the problems in the actual design process.)
- 2018-05-30 13:44:03下载
- 积分:1
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VHDL手册很不错,适合硬件描述语言指南
VHDL handbook is very nice and suitable guide to HVDL language
- 2022-04-17 19:38:41下载
- 积分:1
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VLSIrtl_spi
说明: verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.(Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.)
- 2021-05-13 13:30:02下载
- 积分:1
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buffer
用verilog实现的buffer,经过了fpga平台验证。(Implement buffer with verilog.)
- 2020-10-28 12:19:58下载
- 积分:1