网站首页

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...

于 2022-04-07 发布文件大小:2.15 MB

 0  86

下载积分: 2 下载次数: 1

我要下载

代码说明：

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

TOFED_Dataflow
Take its complement by applying DeMorgan’s theorem to obtain F in the form of product of complemented products.

2014-11-08 06:56:35下载

积分：1
本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块...
本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块-This procedure is a VHDL language electronic code lock function, the entire system is divided into three modules, one for the control module, two for the keyboard display module, three modules for the treatment

2022-05-08 19:29:46下载

积分：1
AD9226_easy
基于赛林思FPGA芯片，控制采集芯片AD9226的程序(FPGA control AD9226 program)

2020-12-06 21:09:22下载

积分：1
简单的APB I2S接口
简单的apb i2s接口，verilog代码，包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)

2019-01-18 16:52:05下载

积分：1
基于FPGA的DDS
基于FPGA的DDS。可以产生三种波形：正弦，方波，三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。(FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.)

2013-08-05 07:06:22下载

积分：1
如何在语言 VHDL 实现液晶显示中显示的数据转移
如何在语言 VHDL 实现液晶显示中显示的数据转移

2023-04-29 11:00:03下载

积分：1
data_rom
正弦信号发生器，用VHDL来完成，抗干扰能力较强，(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)

2009-07-15 22:44:02下载

积分：1
LMS_filter
这是自适应滤波器，使用verilog代码来编写的，已通过了仿真，效果很好。希望能给大家好好分享！(This adaptive filter verilog code to write, through a simulation, with good results. I hope to give a good share!)

2020-12-08 21:19:19下载

积分：1
analogue-digi-ana-converter
design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.

2009-08-04 21:23:05下载

积分：1
T200071012217h
此源码为线性相位滤波的vhdl源码与设计心的体会，理论分分析与工程实践总结相结合，有非常大的参考价值可直接使用。 (The source for the linear phase filter VHDL source code and design of the heart experience, theoretical analysis to summarize the combination of engineering practice, a very large reference value can be used directly.)

2012-07-10 16:08:08下载

积分：1

696518资源总数
105547会员总数
4今日下载

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...

0 个回复

热门标签

热门下载