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a
说明： 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分：1
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BPSK
BINARY PHASE SHIFT KEYING
- 2014-08-20 17:35:44下载
- 积分：1
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fdd
按键消抖，对时钟沿计数决定是否将bin值给内部的按键值。(Debounced buttons, whether on the edge of the clock count within the bin value to the key value.)
- 2011-11-08 14:34:08下载
- 积分：1
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yuanchengxu
基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)
- 2011-11-19 13:36:54下载
- 积分：1
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方形伺服电机 vhdl
PROGRAMM有助于使40厘米见方与FPGA机器人改变board.The运动遵循顺时针旋转。此外，惯性中心的旋转过程中保持不动。
- 2022-02-14 00:56:00下载
- 积分：1
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不足20元的PCI设计，含ABEL源代码。
不足20元的PCI设计，含ABEL源代码。-PCI design less than 20Yuan ,including ABEL code
- 2022-01-24 17:08:50下载
- 积分：1
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fft
说明： 用FPGA实现8点fft，整个代码使用verilog编写，主要运用了加法器和乘法器，简单易懂(8-point FFT with FPGA, The whole code is written by Verilog, mainly using adder and multiplier, which is easy to understand)
- 2021-03-29 20:59:10下载
- 积分：1
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PCI_PIO
不足20元的PCI设计，含ABEL源代码。(PCI design less than 20Yuan ,including ABEL code)
- 2005-08-28 02:44:26下载
- 积分：1
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一个8位处理器结构，源码分析
说明： 关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试(on an eight processors, and source code, VHDL design, the test)
- 2005-12-27 21:39:45下载
- 积分：1
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author: Richard Herveille
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman)
-- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr
-- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-
- 2022-03-20 23:45:27下载
- 积分：1
