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一个基于C51指令系统的简易uCOS示范程序,有完整的代码分析
一个基于C51指令系统的简易uCOS示范程序,有完整的代码分析-A command system based on the C51 model uCOS summary procedures, have a complete code analysis
- 2022-06-01 23:18:00下载
- 积分：1
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Lab2
Simple ALU
Objectives
1. Explore simple ALU structure.
2. Working with components
3. Working with language templates in ModelSim
4. Making a test bench and simulation using ModelSim
- 2017-01-13 19:28:54下载
- 积分：1
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ADPCM
说明： APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)
- 2009-08-22 10:07:03下载
- 积分：1
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VHDL3
说明： 一个使用VHDL进行正弦波信号产生的历程，非常有用。(A sine wave signal generator using VHDL for the course, very useful.)
- 2010-03-27 09:18:41下载
- 积分：1
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源实现YUV到RGB的转换
THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB
- 2022-06-16 04:19:46下载
- 积分：1
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VHDL-DDS
基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率(FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency)
- 2013-06-27 15:16:15下载
- 积分：1
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Multisim
multisim 程序
使用教程 详细明了清楚(multisim tutorial program uses more clearly understand)
- 2010-09-15 22:56:42下载
- 积分：1
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TLC2543
使用Verilog实现的AD采样，很有用的！(Implemented using Verilog AD sampling, very useful!)
- 2020-11-18 15:59:39下载
- 积分：1
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myDPll
说明： 本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。(I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book )
- 2008-08-29 08:54:53下载
- 积分：1
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VHDL
先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
- 2015-01-04 12:35:54下载
- 积分：1
