-
ISE
设计一4位比较器,画出门级电路图,用verilog语言完成设计。
(Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
- 2015-12-11 21:16:12下载
- 积分：1
-
High Speed dd
(Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig
- 2020-06-24 08:40:01下载
- 积分：1
-
CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
- 2023-04-13 10:55:04下载
- 积分：1
-
Beamforming
基于FPGA的波束形成，包括ad转换，数据存储等部分。。(FPGA-based beamforming, including ad conversion, data storage and other parts. .)
- 2016-04-25 11:12:30下载
- 积分：1
-
基于EDA技术设计4位十进制数字频率计的系统方案
基于EDA技术设计4位十进制数字频率计的系统方案-Based on EDA technology design four decimal system solutions Cymometer
- 2022-03-21 02:07:27下载
- 积分：1
-
In communication systems channel poses an important role. channels can convolve...
In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
and more sevear is such distortion is random.
To handle this, multipath affected channels require Equalizers at receaver end.
such equalizer uses different learning Algorithms for identifying channels continuously.
This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton
It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
- 2022-02-24 17:03:03下载
- 积分：1
-
GMSK调制基带眼图仿真源代码
GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)
- 2020-06-28 11:40:01下载
- 积分：1
-
由VHDL 语言实现的DA0832器利用的是QUARTUES环境已经得到验证
由VHDL 语言实现的DA0832器利用的是QUARTUES环境已经得到验证-By the VHDL language uses the DA0832 is QUARTUES environment has been tested
- 2023-02-01 00:40:03下载
- 积分：1
-
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分：1
-
PS2_kebord_controller
PS2键盘控制器的VHDL源码，用FPGA直接读取键盘的输入并显示。(PS2 keyboard controller VHDL source code, with a direct FPGA to read keyboard input and displayed.)
- 2010-10-15 18:13:27下载
- 积分：1
