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delayline_b
基于延迟线的数字脉冲宽度调制，用于电力电子设备的触发信号产生(puls wide modulator based on delayline)
- 2015-03-10 15:45:01下载
- 积分：1
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telephone-cost-metering
该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分：1
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dotdisplay
16*16点阵横向移动显示！采用QUARTUS II 9.0编译通过！(16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!)
- 2011-11-04 22:14:49下载
- 积分：1
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256M_sdram_OK
改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )
- 2013-12-23 16:15:43下载
- 积分：1
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zhentongbu
ＦＰＧＡ在通信上的运用：基于VHDL的帧同步程序(Application of FPGA in communication: Based on VHDL frame synchronization procedures
)
- 2012-11-28 09:10:05下载
- 积分：1
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Nios_II_uCOS
本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。(The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.)
- 2009-12-18 14:08:40下载
- 积分：1
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简单的键盘接口模块程序
一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分：1
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Xilinx V5 FPGA详细规格、编程FPGA参考，系统设计…
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
- 2022-03-16 03:52:38下载
- 积分：1
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Nios-II
数字电路的设计。以软件方式实现硬件电路，功能强大，开发容易。(Digital circuit design. With software to realize the hardware circuit, powerful, development easy.
)
- 2011-12-03 09:47:56下载
- 积分：1
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CCD_Verilog_1014
基于CPLD器件的线型CCD东芝TCD1501的驱动程序，用verilog语言开发。(CPLD devices based on linear CCD driver Toshiba TCD1501 using Verilog language development.)
- 2016-04-24 12:52:19下载
- 积分：1
