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AM-modulated-learning-ladder
AM modulated learning ladder
- 2015-07-15 09:42:45下载
- 积分：1
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85375524AGC
Matlab agc ʵ
- 2010-04-22 21:54:28下载
- 积分：1
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verilog HDL 写的LMS滤波器
verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
- 2022-05-28 16:08:42下载
- 积分：1
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VHDL
软件式的VHDL学习工具，能帮助你更好的掌握VHDL的应用-VHDL-based software, learning tools, can help you better grasp the application of VHDL
- 2022-07-01 16:13:22下载
- 积分：1
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FPGA-implementation
重点介绍了双线性插值算法和该方法的Ｆ Ｐ ＧＡ硬件实现
方法， 包括图像数据缓冲单元、 插值系数生成单元以及插值计算单元等。(Highlights the bilinear interpolation algorithm and the method of F P GA hardware
The method includes an image data buffer unit, the interpolation coefficient generating unit and an interpolation computing unit and the like.)
- 2021-05-14 18:30:02下载
- 积分：1
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DDS Verilog 代码。包含英文文档说明
DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
- 2022-10-25 06:35:03下载
- 积分：1
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频率计实验程序代码
说明： XC7A35TCSG324-1的Verilog频率计程序，支持十分频，支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)
- 2019-12-24 13:40:45下载
- 积分：1
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Hardware Description Language VHDL of the frequency counter program can be used...
硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.
- 2023-01-23 07:20:04下载
- 积分：1
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整个工程代码
说明： 掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)
- 2019-01-21 17:21:27下载
- 积分：1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分：1
