登录
首页 » VHDL » 数字点阵赛车

数字点阵赛车

于 2022-04-10 发布 文件大小:1.60 MB
0 146
下载积分: 2 下载次数: 1

代码说明:

数字电路点阵赛车,分为开始前5秒倒计时,59秒计时,赛车显示,赛道显示,失败提示,成功提示,移动控制以及总控制等8个模块。实现由3个开关控制点阵赛车在设置好的赛道中前进或左右移动。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • Embedded System multiplier test report including source code language used VHDl
    嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl
    2022-03-26 04:15:28下载
    积分:1
  • pipline_lms_and_rls_verilog
    流水线LMS,和RLS算法的Verilog代码,用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)
    2021-05-06 20:58:37下载
    积分:1
  • And the string conversion of the code is relying on the synchronization state ma...
    这个并串转换代码是依靠同步状态机来实现其控制的。其实并串转换在实际的电路中使用还是比较多的,尤其在通信线路方面的复用和分解方面,原理上就是一个串并转换和并串转换的过程。举个简单的例子,计算机串口发送数据的过程,如果满足发送条件了,其实就是一个并串转换的过程了。好了,废话不说,看代码就是。 -And the string conversion of the code is relying on the synchronization state machine to achieve its control. In fact, string conversion circuit in the actual use of, or more, particularly in the area of communication lines and the decomposition of reuse, the principle is a string and the conversion and the conversion process and string. Here is a simple example, the computer serial port of the process of sending data, if sent to meet the conditions, but in fact is a process of conversion and a string. Well, do not talk nonsense, look at the code is.
    2022-03-29 17:46:13下载
    积分:1
  • spwm
    关于SPWM调制设计VHDL代码 关于SPWM调制设计VHDL代码(SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM)
    2021-03-16 09:19:22下载
    积分:1
  • led1
    说明:  点亮led流水灯,通过调用锁相环,可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)
    2020-06-16 07:00:01下载
    积分:1
  • uart
    一个实用的uart协议模块,使用verilog 实现(A practical uart protocol modules, use verilog to achieve)
    2013-07-25 11:43:34下载
    积分:1
  • jtag
    verilog语言编写的jtag(边界扫描模块),初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)
    2021-04-27 14:38:44下载
    积分:1
  • 6_USB_to_SDHC_Lab
    altera max10 USB demo,使用了phy,把开发板配置成U盘模式(altera max10 USB demo,using PHY device,design a U pan)
    2015-10-22 20:47:49下载
    积分:1
  • 实现spi接口的传输,并多外接EEPROM读写数据
    实现spi接口的传输,并多外接EEPROM读写数据-Spi interface to achieve the transfer, and multiple external EEPROM read and write data
    2022-02-06 14:13:33下载
    积分:1
  • 主要是RS
    主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure
    2022-03-17 15:36:56下载
    积分:1
  • 696518资源总数
  • 106182会员总数
  • 24今日下载