-
uart
串口通信通用模块,FPGA Verilog语言 ise,vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分:1
-
计算机组成原理课设
计算机组成原理课程设计代码,课程设计,计组(Computer organization principle curriculum design code, curriculum design, group calculation)
- 2018-10-31 22:26:09下载
- 积分:1
-
Synopsys 帮助文件 version 200205
Synopsys 帮助文件 version 200205-Synopsys sold version 200205
- 2023-08-02 16:20:05下载
- 积分:1
-
USB_xilinx_vhdl
Giao tiep Univesan ...
- 2020-06-20 03:00:02下载
- 积分:1
-
Verilog很不错的进阶书!看完后对数字模拟集成电路设计有个深入的认识!...
Verilog很不错的进阶书!看完后对数字模拟集成电路设计有个深入的认识!-This book is very important for a designer who wants to design a great digital circuits!
- 2022-03-15 20:34:36下载
- 积分:1
-
1553B的编解码程序是有用的给大家分享分享
1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share
- 2022-07-28 09:59:52下载
- 积分:1
-
mico8_vhdl
mico8 vhdl project lattice出的小资源mcu 256luts 值得学习
- 2022-03-18 14:26:11下载
- 积分:1
-
以VHDL为第一通用代码的N位加法器
32位加法器作为VHDL编写的第一个代码;
- 2023-08-19 21:05:03下载
- 积分:1
-
EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。...
EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
- 2022-10-28 17:25:03下载
- 积分:1
-
gps_lms
本系统用于GPS中频部分的窄带滤波(AD后的数据经过LMS滤波后去掉窄带干扰,可以抑制20dB以上的干扰)(this system can be imply to anti-narrowband-jamming for GPS IF signal, it can degrade 20dB narrowband jamming)
- 2011-08-23 21:06:41下载
- 积分:1