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VHDL实现SPI功能源代码
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
- 2022-01-26 00:50:40下载
- 积分：1
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VHDL硬件描述语言作业
VHDL硬件描述语言作业-VHDL hardware description language operations
- 2022-03-19 16:26:25下载
- 积分：1
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DMA
针对QUARTUS的DMA的VHDL代码实现(DMA Controller Code in VHDL)
- 2009-07-04 23:14:32下载
- 积分：1
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seven_persons
自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)
- 2013-08-10 07:15:06下载
- 积分：1
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vsim
flii adder wave form 3
- 2015-04-27 20:02:44下载
- 积分：1
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CPU-master
说明： misp，五级流水源码，实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)
- 2020-06-16 00:00:07下载
- 积分：1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分：1
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fwwallace
wallace tree multiplier in verrilog
- 2013-03-19 00:15:07下载
- 积分：1
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mac
基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)
- 2017-04-24 10:13:55下载
- 积分：1
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jiaotongdeng
Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)
- 2014-01-13 21:57:00下载
- 积分：1
