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mul_ser12
本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)
- 2011-05-31 14:19:30下载
- 积分：1
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6. For the key to enter a password lock, assuming that reset after the seven lam...
6对于进入密码锁的按键，假设复位后七个灯显示" 0"，使用sw1、sw2 2，然后只要按下并松开sw2，七个灯上就显示" 2"，而只要按下并松开sw1，七个灯上就正确显示值" 1
- 2022-03-11 23:10:49下载
- 积分：1
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lowpass
低通滤波器（由matlab和simulink两种方法实现）源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)
- 2013-03-13 18:36:40下载
- 积分：1
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FPGA讲义适合中等以上读者，主要是FPGA的一些高级应用
FPGA讲义适合中等以上读者，主要是FPGA的一些高级应用-FPGA notes for readers more than moderate, mainly a number of advanced applications FPGA
- 2022-06-16 08:29:17下载
- 积分：1
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DSP 程序的测试 很有用的 仪器上面用的
DSP 程序的测试 很有用的 仪器上面用的-DSP testing procedures very useful in the above apparatus
- 2022-12-27 08:25:03下载
- 积分：1
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JV50128
bios spi flash acer 5740g
- 2013-06-28 18:48:06下载
- 积分：1
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采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件...
采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件-AD using high-speed storage oscilloscope design, based on EP1C3 board GWADDA board storage oscilloscope, which has the documentation
- 2022-03-22 11:22:04下载
- 积分：1
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Toplevel VHDL Structural model of a system containing 8051
Toplevel VHDL Structural model of a system containing 8051
-Toplevel VHDL Structural model of a system containing 8051
- 2022-11-19 06:20:03下载
- 积分：1
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vhdl
vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。(vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.)
- 2012-09-04 15:21:53下载
- 积分：1
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利用AT89C51实现LCD日历电子钟源码
利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source
- 2023-01-24 10:00:03下载
- 积分：1
