登录
首页 » VHDL » VHDL与Verilog的比较

VHDL与Verilog的比较

于 2022-04-14 发布 文件大小:38.90 kB
0 177
下载积分: 2 下载次数: 1

代码说明:

VHDL与Verilog的比较-VHDL and Verilog comparison

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • EDA
    EDA-Verilog 编码原则,初学者必看!-EDA-Verilog coding principles, beginners must-see!
    2022-02-20 01:38:26下载
    积分:1
  • HDLC some relevant documents, HDLC design may be very helpful!
    HDLC的一些相关文档,可能对HDLC设计有很大的帮助!-HDLC some relevant documents, HDLC design may be very helpful!
    2022-10-21 11:55:03下载
    积分:1
  • VHDL language design stopwatch, timer function of the realization, the realizati...
    VHDL语言设计的秒表,实现计时功能,实现报时功能,并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
    2022-09-16 02:55:02下载
    积分:1
  • 用VHDL语言编写的写存储器程序,可下载在FPGA中使用
    用VHDL语言编写的写存储器程序,可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
    2022-06-17 11:46:31下载
    积分:1
  • lisa-vhdl2va
    通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)
    2013-12-12 11:17:18下载
    积分:1
  • 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对一个十字路口的交通灯的控制,包括4个红绿灯...
    使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对一个十字路口的交通灯的控制,包括4个红绿灯和4个2位的数码倒计时器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board to realize a crossroads traffic lights control, including four traffic lights, and four 2-bit digital countdown device.
    2022-08-06 00:18:55下载
    积分:1
  • mux_16bit_sign
    16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)
    2016-05-09 21:48:03下载
    积分:1
  • inc_pid
    基于FPGA的增量式PID设计方法,Matlab、Simulink, Xilinx Block set(Incremental PID FPGA-based design methodology)
    2014-11-03 04:16:19下载
    积分:1
  • lmf
    在ISE下,FPGA产生线性调频信号,并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)
    2018-03-29 15:31:15下载
    积分:1
  • multiply_8_VHDL
    由8 位加法器构成的以时序方式设计的8 位乘法器,采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件,运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)
    2014-04-11 16:58:04下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载