登录
首页 » VHDL » 100例VHDL语言解释,北京理工大学毕业…

100例VHDL语言解释,北京理工大学毕业…

于 2022-04-16 发布 文件大小:103.88 kB
0 65
下载积分: 2 下载次数: 1

代码说明:

VHDL语言100例详解,北京理工大学ASIC研究生出版,这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论


0 个回复

  • Applicable to FPGA
    适用于FPGA的SOPC方面的元器件添加,如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
    2023-06-11 11:30:03下载
    积分:1
  • 8b10b
    8b10b编解码,用于光通信和千兆以太网,verilog编写,已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)
    2021-01-27 09:48:41下载
    积分:1
  • project1source
    sdh帧同步,实现sdh帧搜索,预同步,同步,保护等各态的功能(SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state)
    2012-11-08 11:05:55下载
    积分:1
  • i2s_input
    基于FPGA的i2s接口输入模块设计,其中有原理图和verilog源码,可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)
    2020-12-14 16:49:14下载
    积分:1
  • VHDL.Programming
    这是这本书的第四个版本,现在这个版本不仅提供了VHDL语言的覆盖面,但设计方法的信息,以及。此版本将指导读者通过创建一个VHDL设计的过程中,模拟设计,综合设计,放置和布线设计,使用的重要模拟验证的最终结果,新的技术,称为全速调试,提供了极其快速设计验证。在这个版本的设计,例如已被更新(This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect.)
    2012-04-08 19:36:36下载
    积分:1
  • verilog_DATA_displays
    使用verilog语言,滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)
    2014-01-16 10:49:55下载
    积分:1
  • list_ch06_02_debounce
    Eliminate the program of key bounce
    2012-12-23 00:22:42下载
    积分:1
  • 用VHDL编写的FIR数字滤波器的程序可以用在FPGA工作。
    FIR数字滤波器程序,采用vhdl编写,可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit
    2022-08-15 20:37:14下载
    积分:1
  • verilog-lfsr-master
    说明:  Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
    2020-06-24 21:40:01下载
    积分:1
  • 3X3矩阵乘法的VHDL程序!对初学者有很大帮助!
    3X3矩阵乘法的VHDL程序实现!对初学者有很大的帮助!-3X3 matrix multiplication VHDL program! For beginners is a great help!
    2022-01-26 08:06:59下载
    积分:1
  • 696518资源总数
  • 105205会员总数
  • 10今日下载