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XadcMicroblaze-master
说明: 用zynq实现片内的数模转换,基于最新的zynq平台(zynq xadc on FPGA arm)
- 2020-06-21 12:00:02下载
- 积分:1
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Datasheets
关于ALTERA DE2板上的文档资料,包括应用实例,用户文档和板上常用器件的技术文档(datasheets of ALTERA DE2)
- 2010-03-10 10:14:08下载
- 积分:1
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fir48
48阶FIR滤波器的verilog,包含测试文件(48-order FIR filter verilog, including test paper)
- 2021-04-14 19:58:55下载
- 积分:1
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hardware-description
工程实用观点,简单介绍集成电路的传统设计语言现状。(Practical engineering point of view, the traditional integrated circuit design brief language status.)
- 2010-09-19 11:13:38下载
- 积分:1
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traffic-light-design
基于ISP的交通灯设计,实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)
- 2014-07-12 13:35:31下载
- 积分:1
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MIT_Press_Circuit_Design_with_VHDL_(2004)
circuit design with VHDL e-book MIT Press....
- 2009-05-08 00:33:54下载
- 积分:1
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lvds_ctr_top
说明: 用verilog编写的LVDS接口驱动程序,采用IOSERDES技术实现,经过Spartan6 FPGA调试验证,有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)
- 2020-03-16 10:29:10下载
- 积分:1
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I2C Bus Controller ALTERA the VHDL source code
I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
- 2022-01-25 15:11:56下载
- 积分:1
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frequency_generator
DDS in our camera design
- 2010-02-26 22:21:26下载
- 积分:1
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ffirr_166i
fir低通滤波器 用于dspbuilder pll:25nss data 400khz sin 10.8khz 已通过测试。
(fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)
- 2012-06-10 17:54:50下载
- 积分:1