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用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core....
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.
- 2022-03-30 14:40:42下载
- 积分：1
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Camera-Interface-Overview
主要讲述了数码相机MIPI接口协议说明，工作模式及信号传输原理等(Camera Interface Overview)
- 2014-01-20 22:19:32下载
- 积分：1
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verilog实现的1024位的大数模逆算法，引入RAM作为数据通道
verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
- 2022-12-18 20:35:03下载
- 积分：1
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8位相 加乘法器，具有高速，占用资源较少的优点
8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
- 2023-05-06 21:10:02下载
- 积分：1
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master_slave
AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
- 2019-03-22 22:24:20下载
- 积分：1
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8 位 CPU vhdl实现（含全部源代码）
说明： 这是8位CPU的CVDL代码。CPU 的主要功能是执行指令，控制完成计算机的各项操作，包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计，将重点放在寄存器级，采取较简单的组成模式，以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理，从而完成从指令系统到CPU的设计，并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)
- 2020-12-09 15:49:20下载
- 积分：1
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VHDL language used to achieve a display hours, minutes and seconds of the clock:...
用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.
- 2022-04-27 22:51:31下载
- 积分：1
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由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。...
由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and all the procedures.
- 2023-07-12 15:25:04下载
- 积分：1
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ddr2 controller功能控制,里面有四个模块
ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
- 2022-08-22 19:25:19下载
- 积分：1
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FPGA_LED
FPGA入门点亮一个LED灯，作为FPGA入门级程序(FPGA is)
- 2012-03-26 21:57:27下载
- 积分：1
