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Using VHDL hardware language to achieve the top level of the IIC control procedu...
用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures
- 2022-12-20 20:00:08下载
- 积分:1
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m68000
VHDL code for MC68000
- 2011-06-21 17:17:00下载
- 积分:1
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BCH码的二进制FEC码的译码
应用背景BCH码是一种流行的用于存储和传输系统中使用的纠错码。它增加了一些冗余检查数据到原始数据帧,冗余数据长度取决于校正能力,和所有计算进行在伽罗华域,适用于FPGA。关键技术编码:线性反馈移位寄存器解码器:1。证算有2×T-1型要求。首先得到奇数阶的。计算时间不一多项式分裂。都有生成多项式和多项式T T特征多项式。接收到的数据分别由T多项式分,上对应于2×T-1电力原始元素综合征,是从1到T。其次,即使顺序综合征的计算奇数的2。误差位置多项式计算误码位置多项式是由无逆的BM算法计算。计算迭代最多2×t-1时刻。定义为综合征的顺序是2×T-1。定义V是错误位置多项式的阶为2×T-1。有一些变量在计算。3.error位置搜索中国搜索的方法来找到错误的位置。每一个元素放在伽罗瓦域为该错误位置多项式,如果其结果等于零,则该元素对应于误差位置。搜索可以进行并行以缩短运行时间。
- 2023-02-10 12:45:03下载
- 积分:1
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减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能,可以进行自增和自减计数,其计数周期为2^N(N为二进制...
减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能,可以进行自增和自减计数,其计数周期为2^N(N为二进制位数)。 二、设计原理 输入/输出说明: d:异步置数数据输入; q:当前计数器数据输出; clock:时钟脉冲; count_en:计数器计数使能控制(1:计数/0:停止计数); updown:计数器进行自加/自减运算控制(1:自加/0:自减); load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
- 2022-01-28 03:17:59下载
- 积分:1
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ad5791
在Quartus环境下编写,使用Cyclong系列芯片,配置七通道高精度AD5791,该例子为AD5791的FPGA配置使能代码,包括模拟数据输入模块,复位模块,命令接收是能配置模块。(AD5781,Digital signal convert to Analog signal)
- 2021-04-20 14:28:50下载
- 积分:1
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USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
- 2022-01-25 23:39:51下载
- 积分:1
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dadishu_v1
VHDL实现简单打地鼠游戏机,北邮数电实验(VHDL simple playing hamster games, BUPT number of electric experiment)
- 2020-11-03 13:29:52下载
- 积分:1
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本代码实现了486总线的功能,初学者可以借鉴学习
本代码实现了486总线的功能,初学者可以借鉴学习-This code implements the 486 bus functions, beginners can learn to learn
- 2023-09-05 01:20:03下载
- 积分:1
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DE2_115_TV
这个代码主要实现了基于VHDL的关于TV方面的功能。(This code is the main achievement of the VHDL about aspects of the function based on TV.)
- 2013-03-06 21:49:22下载
- 积分:1
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this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100...
this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-07-15 18:56:36下载
- 积分:1