-
Xilinx V5 FPGA详细规格、编程FPGA参考，系统设计…
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
- 2022-04-28 20:14:22下载
- 积分：1
-
Altera大学计划程序包，基于Nios II的源代码
Altera大学计划程序包，基于Nios II的源代码-Altera University program package, based on the Nios II source code
- 2022-05-30 12:30:33下载
- 积分：1
-
自适应滤波器
由于衍射、散射、反射和稀疏等环境损伤的增加，其后果是信号视线的丧失和干扰。自适应信号处理可以克服这些缺陷。该代码是用甚高速硬件描述语言（VHDL）编写的，用以滤除高频，减少噪声和干扰。
- 2023-07-04 11:00:03下载
- 积分：1
-
SourceFile
PS2键盘实验Verilog HDL代码(PS2 keyboard experiment Verilog HDL code)
- 2008-03-15 01:14:55下载
- 积分：1
-
e2
Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency
- 2014-02-23 02:42:47下载
- 积分：1
-
jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分：1
-
数字信号处理的FPGA实现(第4版)源码
说明： 数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
- 2021-01-16 23:08:50下载
- 积分：1
-
AD9826
AD9826中文说明书 ，对于学习AD9826元件有很大的帮助。(AD9826 Discription in Chinese)
- 2015-04-12 14:22:34下载
- 积分：1
-
用VHDL编写的EPP通信协议，可以同时收发字节
用VHDL编写的EPP通信协议，可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes
- 2022-05-22 02:38:48下载
- 积分：1
-
SHIN12-HJCS
每次开机都将次数加1 并存储到EEPROM。这样就能直观的看到机器的使用次数
用P1口 LED做为显示，次数大于256是将溢出，按复位模拟开机 或者直接通过开关开机(Each boot will add a number of times and stored to the EEPROM. So you can visually see the frequency of use of the machine as with P1 port LED display, the number is greater than 256 will overflow, analog power or press the reset switch power directly through)
- 2013-06-13 21:03:46下载
- 积分：1
