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8bit-cpu
VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)
- 2015-10-16 14:26:34下载
- 积分：1
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QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus...
QuartusII简介手册+中文版
本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中
Quartus II 软件的功能。 不过，本手册并不是 Quartus II 软件的详尽参考手
册。 相反，本手册只是一本指导书，它解释软件的功能以及显示这些功能如
何帮助您进行 FPGA 和 CPLD 设计。-QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus II software for beginners, it provides an overview of programmable logic design in Quartus II software. However, this manual is not the Quartus II software, a detailed reference manual. Instead, this manual is a guide book, which explained the functions of the software and show how these features help you to FPGA and CPLD design.
- 2022-07-12 19:32:51下载
- 积分：1
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vivado_LED_Flow
本例程使用vivado2014.4工具，利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。(This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.)
- 2016-04-19 10:19:07下载
- 积分：1
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一个基于fpga的源程序，对于初始接住的人来说很有帮助
一个基于fpga的源程序，对于初始接住的人来说很有帮助-FPGA-based source for the initial very helpful for those who catch
- 2023-01-04 08:05:03下载
- 积分：1
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基于IIC的EEPROM模型代码
说明： 基于IIC协议的EEPROM模型，可实现串行数据转并行数据，并行数据转串行数据，分为EEPROM模块，EEPROM_WR模块，signal模块，Top模块(The EEPROM model based on IIC protocol can convert serial data to parallel data and parallel data to serial data. It is divided into EEPROM module and EEPROM module_ WR module, signal module, top module)
- 2020-10-02 00:30:24下载
- 积分：1
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11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合...
11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
- 2022-10-31 17:45:02下载
- 积分：1
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循环码的verilog编码程序
(7,4)循环码的verilog编码程序，（7，4）循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)
- 2020-06-27 02:00:02下载
- 积分：1
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intelmirco
INTEL 微处理器 第八版 答案 从第二章开始，奇数偶数的答案都有。(INTEL microprocessor eighth edition answer from the beginning of the second chapter, the answer has odd and even.)
- 2021-01-19 02:38:43下载
- 积分：1
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VHDL tutorial for self studying
VHDL tutorial for self studying
- 2022-08-16 11:48:34下载
- 积分：1
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Four-controllable-counter
说明： 功能是（用Verilog语言的，内有比较详细的注释）：
（1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块).
（2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块.
计数器的功能表
nclr adj_minus 功 能
0 0 复位为0
0 1 递增计数
1 0 递减计数
1 1 暂停计数
(Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)
- 2011-03-01 22:47:51下载
- 积分：1
