-
TIMING LEARNING
TIMING LEARNING -TIMING LEARNING
- 2023-04-26 09:15:03下载
- 积分:1
-
SD_rtl
用verilog实现sd卡读写,亲测可用(Implementation of SD card read and write with Verilog)
- 2020-12-27 21:49:02下载
- 积分:1
-
ad0809
adc0809 转换,verilog代码(adc0809 conversion, verilog code)
- 2020-12-21 11:09:08下载
- 积分:1
-
c_xapp260
xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案,同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用(从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口)设计完整的存储器接口解决方案。(The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing
Warfare and Xilinx solutions, but also explains how to use Xilinx
Software tools and hardware-proven reference designs to be for your own
With (from low-cost DDR SDRAM applications to such as 667 Mb/s
This higher performance DDR2 SDRAM interface) design a complete deposit
Storage device interface solution.)
- 2009-11-03 10:01:20下载
- 积分:1
-
quartus-mult
mult,在quartusII中,以模块输入形式,仿真乘法器mult,得到时序图和功能图(a simulation example of mult)
- 2012-10-17 14:22:11下载
- 积分:1
-
Xilinx_2018_Licenses_Downloadly.ir
Xilinx Licenses 2018
- 2020-06-25 08:20:01下载
- 积分:1
-
count16
说明: 制作16位流水灯,实现LED模块对于拨杆0和1的识别(Making 16-bit pipeline lamp to realize the recognition of dial rod 0 and 1 by LED module)
- 2020-06-24 01:20:02下载
- 积分:1
-
telephone-cost-metering
该程序用来实现电话计时以算取费用,比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分:1
-
fft1024-verilogCODE
fft 1024点verilog代码,适用于基-4的FFT算法描述,使用quartus,modelsim,(fftpoint 1024 verilog code)
- 2020-12-19 01:59:10下载
- 积分:1
-
raised-cosine-filter
代码实现了一个根升余弦成型滤波器,2PAM信号通过此成型滤波器,并且匹配接收,画出了发送和接收波形,验证了代码的正确性。(The code designs a root raised cosine filter,2PAM signal transmitted through the filter and matched using the same filter, I plot the transmitted signal and received signal to verify the correctness of the code.)
- 2012-11-09 21:59:53下载
- 积分:1