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EDK_Tutorial_1
EDK tutorial 1 ----------------
- 2013-04-04 10:18:46下载
- 积分:1
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m_ca7
verilog编写的基于CA算法的m序列发生器,其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)
- 2011-10-26 14:33:59下载
- 积分:1
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异步FIFO的设计仿真和综合技术
Simulation and Synthesis Techniques for Asynchronous FIFO Design
- 2022-07-12 03:34:39下载
- 积分:1
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pn_gen_vhd_211
通信中常用的PN序列产生器的源代码全部打包(Communications commonly used in PN sequence generator, the source code of all packaged)
- 2009-02-04 15:41:17下载
- 积分:1
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exp12
说明: 浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)
- 2020-10-09 16:17:35下载
- 积分:1
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moore-FSM
该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)
- 2013-05-10 10:27:09下载
- 积分:1
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dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
- 2023-03-22 17:40:04下载
- 积分:1
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使用VHDL语言编程,烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟...
使用VHDL语言编程,烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
- 2022-06-20 16:23:08下载
- 积分:1
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NIOS II IDE 编程, 定时器测试程序,仅供参考。
NIOS II IDE 编程, 定时器测试程序,仅供参考。-NIOS II IDE programming timer testing procedures, for information purposes only.
- 2022-06-26 06:07:20下载
- 积分:1
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frequency
基于FPGA的频率测量,能测量方波信号的频率、占空比、相位差。范围100mHz~200MHz,精度0.0001Hz(The frequency measurement based on FPGA can measure the frequency, duty cycle and phase difference of the square wave signal. Range 100mHz~200MHz, precision 0.0001Hz)
- 2018-06-29 16:48:41下载
- 积分:1