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实验九 计算机核心（CPU+RAM）的设计与实现
计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)
- 2018-06-09 11:13:43下载
- 积分：1
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a
说明： 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分：1
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赛灵思XC2C256频率计的Verilog实现。mt10t7 7
Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
- 2022-03-26 03:57:37下载
- 积分：1
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电子密码锁
电子密码锁-Electronic Code Lock
- 2022-09-25 17:35:03下载
- 积分：1
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xapp585
LVDS并行数据传输，来自XILINX官网(LVDS Parallel Data Transfer)
- 2020-06-29 08:20:02下载
- 积分：1
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ahb 总线协议
本文以 VHDL 语言编码得到了 AMBA 与 AHB 总线仲裁。这里在本文中，我们设计了 AMBA 总线协议，将用于多奴隶通信环境，多主
- 2022-01-25 21:18:17下载
- 积分：1
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680605rece_7E
hdlc协议的相关程序，用verilog语言编写，供大家交流学习(hdlc protocol procedures using Verilog language for the exchange of learning)
- 2013-01-18 00:53:58下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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DI-S-AND-V
这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem
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- 2015-01-12 12:56:26下载
- 积分：1
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STOPWATCH
STOPWATCH FPGA SEVEN SEGMENT DISPLAY
- 2014-04-16 11:08:57下载
- 积分：1
