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同步FIFO功能,通过Modelsim仿真Verilog语言描述6…
同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated
- 2022-03-24 20:37:31下载
- 积分:1
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bit
// Data port, granularity 8
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined-//-*- Mode: Verilog-*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISH
- 2023-03-16 01:05:04下载
- 积分:1
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ldpc-for-fpga-decoding
ldpc译码算法的matlab实现,码长960,码率1/2,完全模拟fpga硬件实现语言,量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)
- 2021-04-12 21:38:56下载
- 积分:1
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- 2022-01-26 04:29:06下载
- 积分:1
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RotaryEncoder
基于xilinx spartan 3E开发板,通过旋转编码器实现流水灯的左右移动闪烁变换。(Based on the Xilinx Spartan 3E development board, the left and right flicker transformation of the flow lamp is realized by the rotary encoder.)
- 2018-02-05 11:37:43下载
- 积分:1
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DWT-VHDL
小波变换的VHDL代码,内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)
- 2010-05-14 20:37:27下载
- 积分:1
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基于VHDL的多功能调制解调器设计
调制解调器是在发送端通过调制将数字信号转换成模拟信号,而在接收端通过解调将模拟信号转换为数字信号的一种装置。这个程序用VHDL语言编写,实现了二进制振幅键控(2ASK)的调制与解调;二进制频移键控(2FSK)的调制与解调,二进制相位键控(2PSK)的调制与解调过程。
- 2023-09-01 14:05:04下载
- 积分:1
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ccd
自己写的一个tcd1209d的时序驱动代码,是用verilog语言编写的,可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)
- 2021-04-08 09:39:00下载
- 积分:1
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周立公Verilog
关于verilog的知识点和关键点的总结(Summary of knowledge points and key points of Verilog)
- 2020-07-01 22:20:02下载
- 积分:1
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在EFF的代码地址异步FIFO的灰色代码详细设计…
详细设计了异步fifo格雷码中地址码的生效和Man标志的出现
- 2022-02-07 05:32:22下载
- 积分:1