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Realize with a clock input, can realize multi
实现同一个时钟输入,可以实现多分频,在一个时钟的驱动下-Realize with a clock input, can realize multi-frequency, in a clock-driven
- 2023-02-21 01:50:03下载
- 积分：1
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shizhong
VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分：1
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FPGA实现CAN总线控制器源码
说明： 参照can芯片 saj1000控制器结构，写的can控制器(According to the structure of can chip saj1000 controller, the CAN controller is written)
- 2021-01-19 21:38:41下载
- 积分：1
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Copy
说明： this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device
- 2020-06-21 21:00:02下载
- 积分：1
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7_to_1-LVDS-dispaly-from-FLASH
该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕(The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and support for reading data the FLASH BMP images and real-time display to the LCS screen)
- 2016-02-18 14:06:22下载
- 积分：1
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W5100
使用spi模式初始化w5100，实现了快速以太网的初步建立(Using the spi mode initialization w5100, to achieve the initial establishment of a Fast Ethernet)
- 2020-08-02 20:08:35下载
- 积分：1
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ar0134_1280x720P60
Camera AR0134详细的寄存器配置，以及配置顺序，可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )
- 2016-05-15 12:16:56下载
- 积分：1
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LightControl
说明： 经典的雷鸟车灯控制电路设计，各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)
- 2011-03-05 09:49:32下载
- 积分：1
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verilog for full_adder
verilog for full_adder
- 2022-06-28 14:23:05下载
- 积分：1
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在ise10.1.3 Xilinx PicoBlaze的应用开发。
Xilinx PicoBlaze application developed in ISE10.1.3.
- 2023-07-28 07:25:03下载
- 积分：1
