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leading-zero
对于32位寄存器前导零个数的计数,一个简单的程序(32 registers a leading zero number of counts, a simple procedure)
- 2012-06-05 16:41:11下载
- 积分:1
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ping
乒乓球游戏,用led灯控制水上乒乓球,选择了控制键进行操作。详细信息请参见自述
- 2023-02-19 03:35:03下载
- 积分:1
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CORDIC_ATAN
使用verilog语言完成了基于cordic算法求反正切的计算,精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)
- 2008-12-24 11:31:00下载
- 积分:1
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数字电子钟
数字电子钟用自拍图像代替了内置图像的石英制作
- 2022-02-01 06:03:40下载
- 积分:1
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2ASK
2ask调制与解调的源代码,经过测试可用(2ask modulation and demodulation source code is available, tested)
- 2012-12-09 21:27:49下载
- 积分:1
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EP2C35开发板官方原理图,是altera的官方资料。是fpga电路设计的很好参考典范。...
EP2C35开发板官方原理图,是altera的官方资料。是fpga电路设计的很好参考典范。-EP2C35 official development board schematics, is altera of official information. Fpga circuit design is a good reference model.
- 2022-07-01 18:31:57下载
- 积分:1
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This is a realization of I2C interface VHDL module, I2C protocol to achieve
这是一个I2C接口的VHDL实现模块,实现I2C协议-This is a realization of I2C interface VHDL module, I2C protocol to achieve
- 2023-08-26 08:25:03下载
- 积分:1
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电梯控制器程序设计与仿真的vhdl源代码
电梯控制器程序设计与仿真的vhdl源代码-Elevator controller design and simulation of vhdl source code
- 2022-04-08 14:05:19下载
- 积分:1
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yuandaima
以GPS为时间基准,实现多传感器器数据同步采集,整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)
- 2014-10-12 19:15:45下载
- 积分:1
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emifa_ram
FPGA与DSP的EMIF通信,EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)
- 2020-12-01 15:49:26下载
- 积分:1