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tiny-dnn-1.0.0a2
说明: 在zedboard上运行的神经网络架构,方便移植。(Run lenet-5 on zedboard)
- 2020-06-23 19:00:02下载
- 积分:1
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MAC
this is a Multiplier and Accumulate (MAC). written in VHDL
- 2010-08-09 23:40:46下载
- 积分:1
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taxi
利用Verilog HDL语言设计了出租车计费器,使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)
- 2011-08-30 08:18:51下载
- 积分:1
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TLC1620
基于FPGA的Verilog语言实现的六十进制计数器(FPGA-based Verilog language implementation of six decimal counter)
- 2015-04-23 16:23:15下载
- 积分:1
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axi slave
axi slave 模型,verilog描述,自己可以根据自己的设计适当修改。基本功能可能存在bug,不过是模型,大家可以自己稍作修改。
- 2022-01-24 17:36:33下载
- 积分:1
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demo6-beep
说明: demo6 蜂鸣器实验
蜂鸣器演奏音乐(demo6 buzzer buzzer experiment playing music)
- 2020-12-27 22:59:02下载
- 积分:1
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uart代码
uart 串口 verilog 含testbench quartus工程 全双工 发送模块 接受模块
- 2022-04-07 03:03:29下载
- 积分:1
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multiply_8_VHDL
由8 位加法器构成的以时序方式设计的8 位乘法器,采用逐项移位相加的方
法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件,运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)
- 2014-04-11 16:58:04下载
- 积分:1
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ml555_block_plus_example_es
说明: 高速FPGA 开发设计资料,包括全部的设计方案和开发例程,可快速入手FPGA设计。(High speed FPGA development and design data, including all the design schemes and development routines, can quickly start FPGA design.)
- 2020-08-03 11:44:12下载
- 积分:1
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Verilog-shift-mulfunction
FPGA verilog 实现任意位宽的移位相乘法,有符号小数或者有符号整数相乘。函数调用方式(FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call
)
- 2014-06-21 17:08:12下载
- 积分:1