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VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的....
VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的.-VHDL state machine design examples, good for the state machine to figure out would be very useful.
- 2022-07-09 03:27:51下载
- 积分：1
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sender的verilog
利用fpga实现
sender的verilog
利用fpga实现-sender using the Verilog FPGA realize
- 2022-05-26 20:43:04下载
- 积分：1
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在quartus软件下用VHDL语言实现DDS，可产生正弦，余弦，方波，三角波以及锯齿波。
在quartus软件下用VHDL语言实现DDS，可产生正弦，余弦，方波，三角波以及锯齿波。-In the Quartus software using VHDL language realize DDS, can generate sine, cosine, square, triangle and sawtooth waves.
- 2023-01-28 08:15:03下载
- 积分：1
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VHDL洗衣机控制器
VHDL 洗衣机程序，可实现定时、报警、洗衣，脱水等等功能。底层为VHDL文件，顶层为电路图连接
- 2023-07-12 00:20:04下载
- 积分：1
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Marquee with a program written in VHDL, and 60 binary counter program, one desig...
一个用VHDL编写的跑马灯程序和60进制计数器的程序，一个是自己设计的一个是老师要求，都在实验箱上验证成功，希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.
- 2022-08-10 07:53:33下载
- 积分：1
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说明： 高速宽带数字调制技术的研究，该论文也是非常经典的，希望对大家有帮助(High-speed broadband digital modulation technology, the paper is also very classic, I hope all of you help)
- 2009-07-03 11:47:02下载
- 积分：1
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i2c
uboot i2c driver code for arm a5 dual core cpu imapx820, which is an soc of infotmic.
- 2012-10-18 21:51:29下载
- 积分：1
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UART(RS232)
用VERILOG语言实现的通用异步串行收发器（RS232收发器），波特率可设置，通讯稳定，已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)
- 2021-04-01 10:59:08下载
- 积分：1
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verilogppt
北航夏宇闻的Verilog的PPT讲稿，挺经典的，适合初学者学习(Northern Xia Yu Wen' s Verilog the PPT script, very classic, suitable for beginners to learn)
- 2011-06-16 11:32:45下载
- 积分：1
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dpll
用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )
- 2014-04-22 08:36:53下载
- 积分：1
