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移位寄存器。verilog VHDL
shift register. vhdl verilog
- 2023-06-29 10:50:03下载
- 积分：1
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系统设计
说明： 基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)
- 2020-06-21 02:00:01下载
- 积分：1
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THS1206
FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。(FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.)
- 2009-07-09 09:08:27下载
- 积分：1
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PWM
通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
- 2020-06-16 13:20:02下载
- 积分：1
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hdb3_VHDL
hdb3 using language VHDL(Indoor using VHDL language)
- 2020-12-01 20:19:27下载
- 积分：1
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ov7670_sdram_vga_sobel
基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。
FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board.
FPGA edge detection)
- 2019-04-23 17:31:00下载
- 积分：1
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the_last
VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)
- 2021-01-21 12:18:42下载
- 积分：1
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FPGA
基于FPGA的电机控制
FPGA-basedMotorControl-FPGA-based motor control FPGA-basedMotorControl
- 2022-04-13 15:15:14下载
- 积分：1
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QDPSKvhd
说明： 基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)
- 2010-04-23 17:30:53下载
- 积分：1
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ADI_HDMI
从FPGA输出到HDMI Tx的verilog 模块。实现完整HDMI图像输出功能。(FPGA output to HDMI Tx module in verilog)
- 2020-12-17 11:09:12下载
- 积分：1
