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rgb2yuv
用VHDL和verilog编写的RGB颜色空间到YUV颜色空间的转换程序, 是FPGA视频处理中的常用程序!(Written in VHDL and verilog using RGB color space to YUV color space conversion process is commonly used in video processing FPGA program!)
- 2010-06-08 22:15:01下载
- 积分：1
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dda
该程序描述了运用FPGA 实现DDA圆弧插补运算(FPGA DDA)
- 2020-11-29 13:09:28下载
- 积分：1
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使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供
初学者参考...
使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供
初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
- 2022-02-12 09:25:12下载
- 积分：1
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main
EP2C35A实验箱基于NIOSII的串行AD_DA编程(EP2C35A experimental box based NIOSII the serial AD_DA programming)
- 2013-04-22 11:18:27下载
- 积分：1
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vga
说明： 实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分：1
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Sensor_CMOS
Code to controlling a Image sensor - CMOS(Code to controlling a Image sensor- CMOS)
- 2009-11-13 03:02:36下载
- 积分：1
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ReliabilityByFORM
first order reliability method
- 2014-07-21 16:59:32下载
- 积分：1
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jiaotongdeng
交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)
- 2013-08-25 10:02:34下载
- 积分：1
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vhdl语言主要描述语句的说明和使用方法，内附例子可供学习提高...
vhdl语言主要描述语句的说明和使用方法，内附例子可供学习提高-VHDL language description of the main description of statements and the use of methods, containing examples for learning improve
- 2022-01-31 14:01:30下载
- 积分：1
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fffffff
如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分：1
