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VGA
说明： 用VERILOG编写的一个可以实现VGA显示的程序.....(Prepared using a VERILOG VGA display program can .....)
- 2011-03-04 12:25:21下载
- 积分：1
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Using VHDL language description of the memory read and write, user
用vhdl语言描写的存储器的读写，通俗易懂，简单实用。-Using VHDL language description of the memory read and write, user-friendly, simple and practical.
- 2022-05-27 15:20:00下载
- 积分：1
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ROM模块，功能在于，是创建一个简易的rom模块
ROM模块，功能在于，是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分：1
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Verilog_HDL源码
Verilog_HDL源码 -Verilog_HDL source Verilog_HD L FOSS Verilog_HDL FO
- 2022-02-21 04:09:44下载
- 积分：1
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67_ellipf
vhdl very good debug release vhdl very good debug release
- 2006-10-22 18:39:48下载
- 积分：1
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BISS-B---Stimulate_OK
BISS-B 源代码。包含传感器模式和寄存器模式(BISS-B source code. Includes sensor mode and register mode)
- 2021-03-15 19:29:22下载
- 积分：1
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通过VGA接口获取视频输出的VHDL代码
vhdl code for obtaining video output through vga port
- 2022-02-04 13:35:30下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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FPGA_SPWM
说明： 此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)
- 2019-02-19 16:12:33下载
- 积分：1
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SeggerEval_LPC2478
emWin 在LPC2478上实现LCD的高性能显示(emWin to achieve high-performance LCD display in the LPC2478)
- 2012-08-04 13:54:29下载
- 积分：1
