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pinlvji
使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)
- 2020-06-18 10:20:02下载
- 积分：1
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test-ram
design ram v8051 for project
- 2013-07-08 23:24:20下载
- 积分：1
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verilog例子很丰富，几个经典的,希望对初学者有所帮助
verilog例子很丰富，几个经典的,希望对初学者有所帮助-verilog examples of very rich, a few classic, and want to be helpful for beginners
- 2023-03-17 19:05:03下载
- 积分：1
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Ultrasound
软件环境：TI的zstack协议栈
硬件：CC2530无线单片机
功能：利用超声波模块实现测距（该模块型号：HC-SR04 在淘宝上非常常见） 可测2厘米到3米距离(Software environment: TI' s zstack protocol stack hardware: CC2530 wireless microcontroller features: use of ultrasonic ranging module (the module Model: HC-SR04 on Taobao very common) can be measured 2 cm to 3 meters)
- 2020-12-28 23:39:02下载
- 积分：1
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9. For the key to enter a password lock, assuming that reset after the seven lam...
9对于输入密码锁的键，假设复位后七个灯显示" 0"，使用sw1、sw2、sw3、sw4 4，只需按下并松开任意sw1、sw2键，使七个灯显示值加" 1"，只要按下并松开任意sw3、sw4，将使七个灯显示值加" 2"
- 2022-10-18 01:25:04下载
- 积分：1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分：1
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Electronic code locks, FPGA
电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password
- 2022-04-06 21:28:08下载
- 积分：1
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quartus
利用拨码开关控制液晶显示器进行十进制数字显示。(DIP switches control the use of liquid crystal display to decimal figures.)
- 2020-11-24 22:49:33下载
- 积分：1
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GAL
有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)
- 2013-07-09 22:50:01下载
- 积分：1
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玩转LVDS_USB
说明： verilog 版本，Xilinx玩转USB3.0，LVDS接口(verilog version,Xilinxplay with USB3.0,LVDS)
- 2021-01-01 16:01:57下载
- 积分：1
