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VIVADO 从此开始-2017.1-265_14090262
VIVADO 从此开始,详细讲解了vivado,FPGA开发工具的使用，对于初学者学习VIVADO工具很有用。(VIVADO from now on, explained in detail the use of vivado, FPGA development tools, for beginners to learn VIVADO tools very useful.)
- 2020-07-16 11:58:49下载
- 积分：1
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lcd_system
LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)
- 2013-07-24 08:58:53下载
- 积分：1
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Walsh
说明： 利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码。。(Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .)
- 2010-04-20 09:55:10下载
- 积分：1
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一种RISC结构8位微控制器的设计与实现
一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller" s 8 Design and Implementation
- 2023-08-07 22:10:06下载
- 积分：1
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ALOHA
this program is a simulation for Aloha
- 2012-11-13 11:38:10下载
- 积分：1
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在USB contreoller CRC5块
crc5 bolck in usb contreoller
- 2022-03-06 23:01:25下载
- 积分：1
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i2c_master_ip_for_nios
i2c master ip for altera nios, add in qsys
- 2018-03-02 14:50:44下载
- 积分：1
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qiangda
基于FPGA的抢答器程序，VHDL 语言描述。(FPGA)
- 2010-11-06 11:13:17下载
- 积分：1
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fskcodec
FSK编码器和译码器,有需要的朋友可以看看！(FSK encoder and decoder, there is a need friends can see!)
- 2014-08-11 21:12:06下载
- 积分：1
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testbench(xilinx)
Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生
激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce
Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)
- 2012-04-18 16:08:25下载
- 积分：1
