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simple code of some kind of base decoder
based on verilog
simple code of some kind of base decoder
based on verilog
- 2022-01-26 06:31:39下载
- 积分：1
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四分频的程序，输出clkout0就是二分频，clkout1是四分频
四分频的程序，输出clkout0就是二分频，clkout1是四分频-Quarter-frequency process, the output clkout0 is two-way, clkout1-fourth the frequency
- 2022-02-15 17:30:06下载
- 积分：1
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UART_generator
UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)
- 2009-12-23 12:10:03下载
- 积分：1
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拔河电路的设计
VHDL拔河电路的设计 基于cyclone V
VHDL拔河电路的设计 基于cyclone V
VHDL巴赫电路的设计 基于cyclone V
VHDL巴赫电路的设计 基于cyclone V
VHDL巴赫电路的设计 基于cyclone V
- 2022-07-16 17:58:29下载
- 积分：1
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-Elliptic
We present elliptic curve cryptography (ECC) coprocessor,
which is dual-field processor with projective
coordinator. We have implemented architecture for scalar
multiplication, which is key operation in elliptic curve
cryptography. Our coprocessor can be adapted both prime field
and binary field, also contains a control unit with 256 bit serial
and parallel operations , which provide integrated highthroughput
with low power consumptions. Our scalar multiplier
architecture operation is perform base on clock rate and produce
better performance in term of time and area compared to similar
works. We used Verilog for programming and synthesized using
Xilinx Vertex II Pro devices. Simulation was done with Modelsim
XE 6.1e, VLSI simulation software from Mentor Graphics
Corporation especially for Xilinx devices.
- 2012-02-09 10:48:50下载
- 积分：1
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inverter chain
说明： 基于HSPICE实现的反相器链，并分析电路延时(Inverter chain based on HSPICE, and analyze circuit delay)
- 2020-04-21 12:55:52下载
- 积分：1
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VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现...
VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
- 2022-03-14 00:36:42下载
- 积分：1
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matlab
matlab file for image contrast..
- 2010-08-18 03:02:21下载
- 积分：1
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ＲＳ编码在ＦＰＧＡ上实现的理论和方法，对设计ＲＳ编码很有帮助，且ＦＯＧＡ资源占有少...
ＲＳ编码在ＦＰＧＡ上实现的理论和方法，对设计ＲＳ编码很有帮助，且ＦＯＧＡ资源占有少-RS coding in the FPGA to achieve the theory and method useful for design RS encoding, and possession of less FOGA resources
- 2022-05-07 12:16:18下载
- 积分：1
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Using Verilog to write a serial transmission to the parallel transmission of the...
一个用verilog写的串行传输到并行传输的程序，在quaters下编的-Using Verilog to write a serial transmission to the parallel transmission of the procedure, under the quaters
- 2022-06-14 12:50:53下载
- 积分：1
