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                        fft64
                        
                          使用两个8点FFT完成64-point FFT(64-point FFT)                         
                            - 2013-01-15 04:57:52下载
- 积分:1
 
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                        counter
                        
                          设计一个十进制计数器模块,输入端口包括 reset、up_enable 和 clk,输出端口为 count
和 bcd,当 reset 有效时(低电平),bcd 和 count 输出清零,当 up_enable 有效时(高电
平),计数模块开始计数(clk 脉冲数),bcd 为计数输出,当计数为 9 时,count 输出一
个脉冲(一个 clk周期的高电平,时间上与“bcd=9”时对齐)(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9"  when aligned))                         
                            - 2013-04-13 19:53:29下载
- 积分:1
 
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                        ZEDBOARD
                        
                          ZEDBOARD的管脚分配图和约束文件,包括PCB图和xdc文件(Pin assignment of ZEDBOARD)                         
                            - 2021-03-23 21:19:15下载
- 积分:1
 
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                        Verilog-learning-experience
                        
                          初学学习verilog的经验,可以帮助新手以正确的思维方式,学习方法学习。(Verilog learning experience)                         
                            - 2013-09-30 09:51:04下载
- 积分:1
 
- 
                        0_09_uart_tx
                        
                          说明:  在FPGA板卡上面,通过单个按键实现串口的发送功能,带仿真需要自行修改一下工程配置(On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation)                         
                            - 2020-03-26 08:40:39下载
- 积分:1
 
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                        simpleCpu
                        
                          relative cpu design implementation                         
                            - 2013-08-14 21:22:39下载
- 积分:1
 
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                        MapCG
                        
                          cpu与GPU协同计算一个同时支持GPU与CPU的MapReduce框架实现(cpu and GPU collaborative computing)                         
                            - 2014-12-04 23:06:54下载
- 积分:1
 
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                        SRAM6bit
                        
                          sram 6bit仿真模型,verilog编写(sram 6bit simulation model, verilog prepared)                         
                            - 2021-03-16 13:59:22下载
- 积分:1
 
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                        温度补偿的bp神经网络实现
                        
                          使用不怕神经网络做硬件加速,实现温度补偿                         
                            - 2023-08-13 09:50:03下载
- 积分:1
 
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                        line_four
                        
                          利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)                         
                            - 2020-12-01 14:59:27下载
- 积分:1