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十六进制7Segment时钟
十六进制计数器递增 ALTERA FPGA 板 7 段显示器上的每一秒。
- 2022-07-13 21:46:37下载
- 积分：1
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master and slave code
集成电路的规模日益扩大
- 2022-03-02 13:07:25下载
- 积分：1
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1
一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
- 2013-12-24 09:19:13下载
- 积分：1
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HDMI
说明： 包括HDMI和DVI的源文件，以及相应打仿真文件(Including HDMI and DVI source files, as well as the corresponding simulation files)
- 2020-08-26 20:58:26下载
- 积分：1
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ADC-Parameter
外部ADC采集数据，存为数组文件。通过程序读入，然后即可求出ADC的SNR、SINAD、THD、ENOB等。(External ADC data collection, stored as an array of documents. Read through the program, then the ADC SNR, SINAD, THD, ENOB can be calculated.)
- 2021-03-15 21:39:22下载
- 积分：1
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verilog写的数字频率计的控制模块,对程序进行控制
verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control
- 2022-02-04 00:52:27下载
- 积分：1
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32 floating
32位元浮点CPU,用VHDL语言以类似组合语言的方式写成-32 floating-point CPU(VHDL)
- 2022-10-02 18:30:03下载
- 积分：1
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emif_tt
实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)
- 2020-12-04 15:59:23下载
- 积分：1
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ep2c5 实现 逻辑门
verilog语言，quartus 2 仿真
ep2c5 实现 逻辑门
verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation
- 2022-09-08 22:10:08下载
- 积分：1
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i2c bus project implementation can be used in altera verification environment
i2c总线的工程实现，可以用在altera环境下验证-i2c bus project implementation can be used in altera verification environment
- 2022-04-29 14:30:18下载
- 积分：1
