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主要是RS
主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure
- 2022-03-17 15:36:56下载
- 积分:1
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ccd
自己写的一个tcd1209d的时序驱动代码,是用verilog语言编写的,可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)
- 2021-04-08 09:39:00下载
- 积分:1
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master and slave code
集成电路的规模日益扩大
- 2022-03-02 13:07:25下载
- 积分:1
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sim
csapp 第二版 体系结构实验 答案 第三个部分能跑58分(the second edition csapp architecture experiment the third part of the answer can run 58 minutes)
- 2013-05-20 10:28:00下载
- 积分:1
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8b10bEncoderDecoder-SourceCode (1)
lattice的官方8b10b代码, 1012年版本,diamond3.5编译。(lattice 8b10b encoder decoder code)
- 2020-08-31 14:58:10下载
- 积分:1
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iir
八阶巴特沃兹iir数字滤波器,四个二阶节,verilog代码实现,多路分时复用(batterworth,iir,8order,four second order section)
- 2016-01-27 19:49:47下载
- 积分:1
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FPGA开发全攻略
FPGA设计攻略及流程,包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
- 2017-12-12 16:30:52下载
- 积分:1
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这是一个简单的除法器(32bit/16bit),采用移位相减法
这是一个简单的除法器(32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
- 2022-07-06 17:00:38下载
- 积分:1
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DE2_70_Control_Panel_v1.3.0
DE2-70开发板中附带的控制面板,可以读取存储器中的数据,这个可以正常连接和读取,有好几版本的,有的不能用,而这个经过我亲自测试。(DE2-70 development board comes with a control panel, you can read the data in the memory, this can be properly connected and read, there are several versions, and some can not be used, and this after I personally tested.)
- 2012-10-06 22:29:11下载
- 积分:1
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vga_driver
verilog语言设计的VGA驱动。在Quarus11.0下编译成功,并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)
- 2016-05-25 17:19:18下载
- 积分:1