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code
涉及到常用的模块，参数可配置，可以很方便的集成到应用中(Related to commonly used modules, parameters can be configured, can be easily integrated into applications)
- 2008-06-13 22:30:14下载
- 积分：1
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本文件是周立功试验开发板的配套资料，容易学会
本文件是周立功试验开发板的配套资料，容易学会-This document is ZLG test development board supporting information, easy to learn
- 2023-03-21 03:05:05下载
- 积分：1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分：1
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程序
说明： 传感器是一种检测装置，能感受到被测量的信息，并能将感受到的信息，按一定规律变换成为电信号或其他所需形式的信息输出，以满足信息的传输、处理、存储、显示、记录和控制等要求(Sensor is a kind of detection device, which can sense the measured information and transform it into electrical signal or other required information output according to certain rules to meet the requirements of information transmission, processing, storage, display, recording and control.)
- 2020-06-18 22:00:01下载
- 积分：1
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通用：我新的FFT VHDL VHDL，我试图用Xilinx的FFT核，但当…
FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity o
- 2022-06-20 20:06:05下载
- 积分：1
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UART Basic, hardwired RS232 UART.
--##############################################################################
- 2023-05-28 14:35:03下载
- 积分：1
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CPU-Verilog
简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分：1
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n_bit_counter
n bit generic shift registers
- 2011-03-18 17:55:19下载
- 积分：1
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用FPGA实现CRC算法，只用一个脉冲就能实现，比传统的移位算法大大节约时间...
用FPGA实现CRC算法，只用一个脉冲就能实现，比传统的移位算法大大节约时间-Using FPGA to achieve CRC algorithm, only one pulse will be able to realize, than the traditional algorithm greatly saving time shift
- 2022-07-14 15:39:31下载
- 积分：1
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本书详细介绍了VHDL硬件描述语言，希望在以后的工作中能用到...
本书详细介绍了VHDL硬件描述语言，希望在以后的工作中能用到-This book details the VHDL hardware description language, want to work in the future can be used to
- 2022-05-25 00:38:07下载
- 积分：1
