-
简单的APB I2S接口
简单的apb i2s接口,verilog代码,包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)
- 2019-01-18 16:52:05下载
- 积分:1
-
04_uart_test
说明: 基于FPGA的串口发送和接收,使用的verlilog语言(Using Verilog serial port program, send and receive.)
- 2020-10-13 10:33:10下载
- 积分:1
-
verilog_rtl
关于LDPC解码的verilog程序,包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)
- 2015-10-29 15:42:03下载
- 积分:1
-
7位数码管的显示
实现7位数码管的显示,可以优先解决用户很多问题,不懂得可以问我,不用客气,7位数码管的显示很简单的
- 2023-06-09 10:50:03下载
- 积分:1
-
frenqucy
利用康芯公司的FPGA芯片设计制作频率计,实现对频率的测量。(Kang core using FPGA chip design company frequency meter, realize the frequency measurements.)
- 2011-07-27 15:49:30下载
- 积分:1
-
AHB_UVC_and_AHB_IC_Verificat
ahb uvc is an on chip communication protocol for high speed integration and low power utilities performance protocols widely used in all vip applications
- 2020-10-21 12:07:24下载
- 积分:1
-
Tym605V2Demo
FPGA(赛灵思)试验箱 实验程序 有Audio,Buzzer,key,ledarray,ledseg.......(FPGA(赛灵思)试验箱 实验程序Audio,Buzzer,key,ledarray,ledseg)
- 2012-02-11 21:09:19下载
- 积分:1
-
AMBA_apb
AMBA_APB verilog code
- 2017-08-15 21:05:37下载
- 积分:1
-
hulf
设计一个哈夫曼编码器
要求对一段数据序列进行哈夫曼编码,使得平均码长最短,输出各元素编码和编码后的数据序列。
① 组成序列的元素是[0-9]这10个数字,每个数字其对应的4位二进制数表示。比如5对应0101,9对应1001。
② 输入数据序列的长度为256。
③ 先输出每个元素的编码,然后输出数据序列对应的哈夫曼编码序列。(Designing a Huffman Encoder
Huffman coding is required for a data sequence to minimize the average code length and output the coded and coded data sequence of each element.
(1) The elements that make up the sequence are the 10 digits [0-9], and each digit is represented by its corresponding 4-bit binary number. For example, 5 corresponds to 0101, 9 corresponds to 1001.
(2) The length of the input data sequence is 256.
(3) First output the encoding of each element, and then output the Huffman encoding sequence corresponding to the data sequence.)
- 2019-06-19 21:49:58下载
- 积分:1
-
fht_latest.tar
FAST HADAMARD TRANSFORM VERILOG FOR IMAGE PROCESSING
- 2013-08-19 13:47:40下载
- 积分:1