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子字节的有效执行
应用背景此文件包括执行与数学计算的子字节。查找表和组合方法已被包括在内。关键技术Xilinx XC3S400 VHDL编程语言已经使用这些代码。
- 2023-05-26 21:50:03下载
- 积分:1
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XILINX平台DDR3设计教程
从零开始的Xilinx DDR3 控制程序编写教程,利用MIS IP核通过自编逻辑实现对DDR3的读写,强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)
- 2018-06-05 21:28:45下载
- 积分:1
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carry_lookahead_add4
4位的超前进位加法器,门级电路连接得到,verilog代码实现(4-bit look-ahead adder, gate-level circuit)
- 2011-10-18 21:40:20下载
- 积分:1
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And the string conversion of the code is relying on the synchronization state ma...
这个并串转换代码是依靠同步状态机来实现其控制的。其实并串转换在实际的电路中使用还是比较多的,尤其在通信线路方面的复用和分解方面,原理上就是一个串并转换和并串转换的过程。举个简单的例子,计算机串口发送数据的过程,如果满足发送条件了,其实就是一个并串转换的过程了。好了,废话不说,看代码就是。
-And the string conversion of the code is relying on the synchronization state machine to achieve its control. In fact, string conversion circuit in the actual use of, or more, particularly in the area of communication lines and the decomposition of reuse, the principle is a string and the conversion and the conversion process and string. Here is a simple example, the computer serial port of the process of sending data, if sent to meet the conditions, but in fact is a process of conversion and a string. Well, do not talk nonsense, look at the code is.
- 2022-03-29 17:46:13下载
- 积分:1
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海力士公司8M字节的SDR SDRAM实现Verilog仿真语言。
Hynix公司8M byte sdr sdram的verilog语言仿真实现。-Hynix company 8M byte sdr sdram realize the Verilog simulation language.
- 2023-07-14 06:05:04下载
- 积分:1
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VHDL手册很不错,适合硬件描述语言指南
VHDL handbook is very nice and suitable guide to HVDL language
- 2022-04-17 19:38:41下载
- 积分:1
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ADS1115
本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型,16位,为IIC通信方式,调试较复杂,在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)
- 2013-08-23 22:49:26下载
- 积分:1
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IIC controller for Sopc Builder
IIC控制器 for Sopc Builder-IIC controller for Sopc Builder
- 2022-05-21 02:21:43下载
- 积分:1
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二进制除法器,采用移位相减的方法实现,位数可调
二进制除法器,采用移位相减的方法实现,位数可调-The source code of a divider
- 2023-08-14 00:00:02下载
- 积分:1
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digital_clock
说明: 数字钟通过verilog实现,并且支持Modelsim仿真,通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分:1