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ahb_verilog_design
代码为ahb interface ，用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)
- 2020-12-21 14:49:07下载
- 积分：1
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GBT-15946-2008GPIB
GBT 15946-2008 GPIB可编程仪器标准数字接口的高性能协议 概述 (GBT 15946-2008 GPIB Programmable Instruments standard digital interface for high-performance protocol Overview)
- 2012-08-30 11:49:29下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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UART
基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)
- 2020-06-18 23:20:01下载
- 积分：1
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USB 1.1 IP
USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
- 2022-05-24 18:47:17下载
- 积分：1
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ram2fifo
异步fifo实现，通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)
- 2018-09-21 09:25:35下载
- 积分：1
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LFM
该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
- 2021-04-19 09:38:51下载
- 积分：1
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CPLD
控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.(Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.)
- 2008-05-26 11:37:38下载
- 积分：1
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8 位 CPU vhdl实现（含全部源代码）
说明： 这是8位CPU的CVDL代码。CPU 的主要功能是执行指令，控制完成计算机的各项操作，包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计，将重点放在寄存器级，采取较简单的组成模式，以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理，从而完成从指令系统到CPU的设计，并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)
- 2020-12-09 15:49:20下载
- 积分：1
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imply logic
由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分：1
