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msk_mod_demod
该程序实现最小频移键控信号的调制解调,经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)
- 2013-10-14 23:02:39下载
- 积分:1
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吠陀乘数
它是一种算法,它是用来在超大规模集成电路的乘法2
- 2022-08-13 05:00:33下载
- 积分:1
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hdlsrc
GMSK vhdl generated from simulink
- 2018-11-12 22:45:36下载
- 积分:1
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数字频率合成原理
就是生成原始波形数据,设计Verilog代码,把数据加载到初始ram中,再调用数据进行仿真,仿真实现波形还原,和进行合成之类。
- 2022-09-27 09:25:08下载
- 积分:1
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exp12
说明: 浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)
- 2020-10-09 16:17:35下载
- 积分:1
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verilog uart 115200
使用verilog编写的串口uart发送模块,发送速率为115200,输入时钟为50m,多年验证无任何错误
- 2022-02-09 17:35:29下载
- 积分:1
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FPGA实现SHA256
利用硬件(可编程逻辑器件FPGA)实现密码算法SHA256,在FPGA中嵌入软核NIOSii,在NIOSii上进行软件编程。硬件EDA工具为ALTERA的Quartus ii,软件IDE为eclipse(嵌在Quartua中)。
- 2022-06-21 07:17:01下载
- 积分:1
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dct
里面含有vhdl和verilog 版本,很好用!dct变换用得很多啊!(Which contains a VHDL and Verilog versions of very good use! Dct transform with a lot ah!)
- 2007-08-27 16:00:31下载
- 积分:1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号,在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯,数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分:1
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05_fifo_test
说明: FIFO: First in, First out 代表先进的数据先出,后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO,根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
- 2021-04-08 22:19:20下载
- 积分:1