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uartfifo使用fifo进行uart通信
使用verilog HDL语言进行编写,通过FIFO缓存,使用uart串口,与上位机进行通信。在本示例中,FPGA向上位机发送的数据每次加一,并在串口调试助手中显示,可以观察相关现象。
- 2022-02-21 18:02:35下载
- 积分:1
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UART(RS232)
用VERILOG语言实现的通用异步串行收发器(RS232收发器),波特率可设置,通讯稳定,已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)
- 2021-04-01 10:59:08下载
- 积分:1
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Verilog-learning-experience
初学学习verilog的经验,可以帮助新手以正确的思维方式,学习方法学习。(Verilog learning experience)
- 2013-09-30 09:51:04下载
- 积分:1
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emif_tt
实现dsp与fpga的emif的verilog异步实现,可实现异步读写以及相应功能模块控制,文件中包含仿真后的波形图形以及仿真测试程序,运行环境quartus ii11.0,仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)
- 2020-12-04 15:59:23下载
- 积分:1
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20190717 - Copy
说明: this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分:1
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27个FPGA实例源代码
一些对初学者比较实用的源码,ASK,PSK,FSK调制解调(Some of the more practical source code for beginners)
- 2020-12-10 16:29:20下载
- 积分:1
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bcdadd
4-Bit BCD Adder in Verilog
- 2014-03-26 09:29:21下载
- 积分:1
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DVI&Bt1120
BT1120和DVI标准协议,分析了BT1120的视频书写格式,和DVI的编码格式(BT1120 and DVI standard protocol)
- 2018-01-26 18:06:09下载
- 积分:1
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VHDL
用VHDL语言实现一Mealy型时序电路,并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)
- 2014-03-20 14:44:28下载
- 积分:1
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clock
EDA用maxplus2开发设计的简易数字钟,适合初学者,vhdL语言(EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language
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- 2011-10-03 20:50:23下载
- 积分:1