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VHDL_modelling_guidelines是vhdl建模开发的指导资料
VHDL_modelling_guidelines是vhdl建模开发的指导资料-VHDL modeling VHDL_modelling_guidelines is guiding the development of information
- 2022-03-12 23:37:10下载
- 积分:1
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FPGA的I2S接收模块 audio_in_buff
说明: 用于FPGA的I2S接收模块,仅供学习和参考(audio-i2s receive.use fpga.)
- 2019-04-21 12:11:23下载
- 积分:1
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dft
verilog语言实在点变换DFT源代码,可以配合软核或者其他CPU进行综合FFT变换,也可以单独使用生成module!(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)
- 2009-05-09 14:29:47下载
- 积分:1
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一个可以综合的Verilog 写的FIFO存储器
内附文档说明
一个可以综合的Verilog 写的FIFO存储器
内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
- 2022-03-13 18:19:46下载
- 积分:1
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使用VHDL语言,对Altera公司的DE2开发板进行开发,本例实现了对板上7段数码管的显示,在niosiiIDE上基于硬件实现小灯的循环亮灭...
使用VHDL语言,对Altera公司的DE2开发板进行开发,本例实现了对板上7段数码管的显示,在niosiiIDE上基于硬件实现小灯的循环亮灭-Using VHDL language, on Altera s DE2 development board for development, which in this case the realization of paragraph 7 of the on-board digital tube display, in niosiiIDE hardware implementation based on a small circle of bright lights out
- 2022-03-17 06:00:39下载
- 积分:1
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用vlog语言编制程序CPU控制器源代码…
用vlog语言编写的cpu控制器源代码,用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
- 2022-02-15 12:37:59下载
- 积分:1
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full adder in vhdl of 4 bits
full adder in vhdl of 4 bits
- 2022-02-01 04:44:39下载
- 积分:1
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8051core
8051core-Verilog FPGA的51单片机内核源代码!
-8051core-Verilog FPGA 51 Singlechip kernel source code!
- 2023-02-06 02:20:03下载
- 积分:1
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jishi
计时器=================(Timer =================)
- 2009-12-27 21:41:10下载
- 积分:1
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aurora_IP
Aurora协议是一款高带宽、低成本、可扩展、框架简洁、适合点对点串行数据传输的协议。(Aurora protocol is a high-bandwidth, low-cost, scalable, simple framework for point to point serial data transfer protocol.)
- 2017-03-10 17:16:22下载
- 积分:1