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This is the design of the divider module EDA. Can achieve three different freque...
此为EDA设计的分频器模块。可以实现三种不同的频率信号，可以通过使用者自由设置频率大小-This is the design of the divider module EDA. Can achieve three different frequency signals, users can freely set the frequency of the size of
- 2022-07-22 16:48:57下载
- 积分：1
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41_eth_ddr3_lcd
说明： “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)
- 2021-03-21 00:33:00下载
- 积分：1
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fpga1394
这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.(This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.)
- 2005-03-31 16:09:51下载
- 积分：1
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VerilogHDL_advanced_digital_design_code_Ch6
VerilogHDL_advanced_digital_design_code_Ch6
Verilog HDL 高级数字设计源码ch6(Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch6Verilog HDL source CH6)
- 2007-11-27 10:13:37下载
- 积分：1
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steper motor
说明： stepper motor module on spartan 6 and 24MHz clock fequency
- 2019-03-10 15:44:31下载
- 积分：1
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zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分：1
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blessing3.9.6
Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。
使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。
合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。
(Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1.
Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually.
Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)
- 2015-04-15 22:45:03下载
- 积分：1
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TFT_CTRL_800_480_16bit
说明： 文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
- 2019-04-12 09:22:29下载
- 积分：1
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VHDL
VHDL上百实例 包括 ADDER LATCH FIPPER AND ETC..(VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..)
- 2010-11-22 05:15:29下载
- 积分：1
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FIR低
fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
- 2023-05-01 00:45:03下载
- 积分：1
