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JIAOTONGDENG
用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分：1
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EDA very important small procedures to ensure that key reliability and prevent j...
EDA中很重要的小程序，保证按键可靠性，防止抖动误差信号产生，外部信号输入时必用此消抖函数-EDA very important small procedures to ensure that key reliability and prevent jitter error signal generated, the external input signal must use this function Consumers shiver
- 2022-02-13 11:15:40下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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Typical examples of character LCD interface 10.8 The Design and Implementation o...
典型实例10.8 字符LCD接口的设计与实现
软件开发环境：ISE 7.1i
硬件开发环境：红色飓风II代－Xilinx版
1. 本实例控制开发板上面的LCD的显示；
2. 工程在project文件夹里面
3. 源文件和管脚分配在
tl文件夹里面
4. 下载文件在download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects project folder inside 3. the distribution of the source file and pin in rtl folder inside 4. download files in download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
- 2022-07-15 02:45:21下载
- 积分：1
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this is the for a equiripple filter
this the for a equiripple filter-this is the for a equiripple filter
- 2022-04-17 20:07:48下载
- 积分：1
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dac8568
Verilog 语言写的控制 DAC8568 的模块，DAC8568 是SPI接口。(Verilog language used to write the control module DAC8568, DAC8568 is SPI interface.)
- 2015-10-30 18:02:04下载
- 积分：1
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Continuous_acoustic_emission_board
多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)
- 2020-06-25 13:00:01下载
- 积分：1
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dma_hussam
verilog code for dma
- 2021-04-24 19:09:04下载
- 积分：1
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在USB contreoller CRC5块
crc5 bolck in usb contreoller
- 2022-03-06 23:01:25下载
- 积分：1
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Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
- 2020-12-18 09:49:10下载
- 积分：1
