-
ModelSim-gaojishiyong--Camp
FPGA开发仿真工具modelsim的高级进阶教程，包括如何写脚本文件和后台批处理文件(FPGA Development Advanced simulation tools modelsim tutorial, including how to write a script file and back-office batch file)
- 2012-05-09 23:52:21下载
- 积分：1
-
8051core-Verilog
用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！(Verilog FPGA internal 8051 core, super, super hard to find! Shared out!)
- 2020-06-28 22:00:02下载
- 积分：1
-
ControlUnit
Control Unit VHDL code. Xilinx Spartan 3E board
- 2012-03-15 13:29:40下载
- 积分：1
-
05_key_test
说明： 利用FPGA实现对外设按键的控制，例如用户库用按键控制跑马灯的效果(FPGA is used to realize the control of external keys, such as the effect of user database using keys to control the running horse lamp)
- 2020-06-16 10:00:11下载
- 积分：1
-
cordic算法verilog实现代码
采用verilog编写的经典的cordic算法，旋转模式，亲测可用，经过了9次旋转。cordic算法采用不断旋转求出正弦余弦值，是一种有效地迭代算法
- 2022-07-04 20:40:51下载
- 积分：1
-
红外
说明： 一个红外遥控，可以学习其他的红外编码，并存储记忆，并且将学习到的编码发送(An infrared remote control)
- 2020-06-25 10:27:32下载
- 积分：1
-
6
说明： 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。
设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。
输入：连续脉冲，逻辑开关；输出：七段LED。
(4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously.
Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output.
Input: Continuous pulse, logic switches output: seven-segment LED.)
- 2010-06-21 22:07:59下载
- 积分：1
-
cordic_atan
说明： 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。
鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。(Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.)
- 2010-04-07 16:30:47下载
- 积分：1
-
uart_rx
uart接收模块
// 波特率：9600
// 数据位：8
// 停止位：1
// 校验位：0(UART receive module
Baud rate: 9600 /
/ / data: 8
/ / stop: 1
/ / check digit: 0)
- 2017-07-10 13:56:54下载
- 积分：1
-
dac5686
在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)
- 2014-09-11 11:05:20下载
- 积分：1
