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BCH_EncDec_Matlab
bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)
- 2011-10-27 21:55:11下载
- 积分：1
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12_lcd12864
本实验是用LCD12864显示英文
显示
Our FPGA EDA
NIOS II
SOPC
FPGA(This experiment is shown in English with LCD12864 display Our FPGA EDA NIOS II SOPC FPGA)
- 2013-06-26 11:35:54下载
- 积分：1
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8阶的FIR的Verilog hdl实现
使用matlab的simulink工具滤波器功能实现了FIR系数的计算，同时使用verilog hdl实现了功能仿真，通过调试在Xilinx的ZEDBOARD板子上实现了结果，使得FIR的应用得以在硬件上实现，调试和注解有写。
- 2022-03-24 14:30:01下载
- 积分：1
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061110061
在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)
- 2010-05-21 20:01:16下载
- 积分：1
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I2S
SMT32F4 i2s 全双工配置，自己测试OK的，大家可以看看(SMT32F4 i2s 全双工配置)
- 2021-03-06 22:29:30下载
- 积分：1
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CDCM6208_SPI
说明： 完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)
- 2021-02-06 18:29:56下载
- 积分：1
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FPGA-based-image-acquisition-system
FPGA-based high-speed image acquisition system
- 2016-10-08 11:24:05下载
- 积分：1
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codic
8级cordic 算法verilog (8 cordic algorithm verilog)
- 2013-08-21 11:31:46下载
- 积分：1
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phone
用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)
- 2020-11-06 13:19:49下载
- 积分：1
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blocking
基于verilog语言的数据选择器，包括数据选择器的测试模块
(verilog language based on the data selector, including data selection for the test module)
- 2007-03-22 09:05:10下载
- 积分：1
