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BT656_RGB
将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)
- 2021-03-22 09:29:17下载
- 积分:1
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DCT_IDCT
DCT and Idct with vhdl and verilog
- 2017-11-22 17:15:12下载
- 积分:1
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宝宝挂
最新热血江湖外挂,需要的可以下载,游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))
- 2020-06-23 09:20:02下载
- 积分:1
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DecimationFilterDesignforDDCandImplementingItwithF
本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB
滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性(This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design)
- 2008-04-14 11:02:00下载
- 积分:1
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liyuanlnx_IP_RAM
FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1
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通用RS编码
RS通用编码器,根据定义的参数以及本原多项式就能实现各种体制的编码,Verilog实现,还附带有限域乘法的实现,代码清晰,精炼
- 2022-08-15 10:45:57下载
- 积分:1
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fir4btp
4tap FIR filter in verilog code
- 2014-01-13 22:30:58下载
- 积分:1
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FPGA+AD7656
说明: FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)
- 2020-10-11 23:27:32下载
- 积分:1
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DDR2_hardcore_userguide
xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)
- 2009-11-23 10:18:28下载
- 积分:1
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ahb slave code
它支持ahb接口它是一个内存模型,当传输完成时给出正常响应,当发现地址超出范围时给出错误响应
- 2022-03-07 13:35:13下载
- 积分:1